#include "arm_opcodes.h"
#include "arm_semihosting.h"
#include "transport/transport.h"
+#include "smp.h"
#include <helper/time_support.h>
-#define foreach_smp_target(pos, head) \
- for (pos = head; (pos != NULL); pos = pos->next)
-
static int cortex_a_poll(struct target *target);
static int cortex_a_debug_entry(struct target *target);
static int cortex_a_restore_context(struct target *target, bool bpwp);
static int cortex_a_init_debug_access(struct target *target)
{
struct armv7a_common *armv7a = target_to_armv7a(target);
+ uint32_t dscr;
int retval;
/* lock memory-mapped access to debug registers to prevent
/* Resync breakpoint registers */
+ /* Enable halt for breakpoint, watchpoint and vector catch */
+ retval = mem_ap_read_atomic_u32(armv7a->debug_ap,
+ armv7a->debug_base + CPUDBG_DSCR, &dscr);
+ if (retval != ERROR_OK)
+ return retval;
+ retval = mem_ap_write_atomic_u32(armv7a->debug_ap,
+ armv7a->debug_base + CPUDBG_DSCR, dscr | DSCR_HALT_DBG_MODE);
+ if (retval != ERROR_OK)
+ return retval;
+
/* Since this is likely called from init or reset, update target state information*/
return cortex_a_poll(target);
}
/* We have a halting debug event */
LOG_DEBUG("Target halted");
target->state = TARGET_HALTED;
- if ((prev_target_state == TARGET_RUNNING)
- || (prev_target_state == TARGET_UNKNOWN)
- || (prev_target_state == TARGET_RESET)) {
- retval = cortex_a_debug_entry(target);
+
+ retval = cortex_a_debug_entry(target);
+ if (retval != ERROR_OK)
+ return retval;
+
+ if (target->smp) {
+ retval = update_halt_gdb(target);
if (retval != ERROR_OK)
return retval;
- if (target->smp) {
- retval = update_halt_gdb(target);
- if (retval != ERROR_OK)
- return retval;
- }
+ }
+ if (prev_target_state == TARGET_DEBUG_RUNNING) {
+ target_call_event_callbacks(target, TARGET_EVENT_DEBUG_HALTED);
+ } else { /* prev_target_state is RUNNING, UNKNOWN or RESET */
if (arm_semihosting(target, &retval) != 0)
return retval;
target_call_event_callbacks(target,
TARGET_EVENT_HALTED);
}
- if (prev_target_state == TARGET_DEBUG_RUNNING) {
- LOG_DEBUG(" ");
-
- retval = cortex_a_debug_entry(target);
- if (retval != ERROR_OK)
- return retval;
- if (target->smp) {
- retval = update_halt_gdb(target);
- if (retval != ERROR_OK)
- return retval;
- }
-
- target_call_event_callbacks(target,
- TARGET_EVENT_DEBUG_HALTED);
- }
}
} else
target->state = TARGET_RUNNING;
if (retval != ERROR_OK)
return retval;
- /*
- * enter halting debug mode
- */
- retval = mem_ap_read_atomic_u32(armv7a->debug_ap,
- armv7a->debug_base + CPUDBG_DSCR, &dscr);
- if (retval != ERROR_OK)
- return retval;
-
- retval = mem_ap_write_atomic_u32(armv7a->debug_ap,
- armv7a->debug_base + CPUDBG_DSCR, dscr | DSCR_HALT_DBG_MODE);
- if (retval != ERROR_OK)
- return retval;
-
int64_t then = timeval_ms();
for (;; ) {
retval = mem_ap_read_atomic_u32(armv7a->debug_ap,
* C_MASKINTS in parallel with disabled interrupts can cause
* local faults to not be taken. */
buf_set_u32(armv7m->core_cache->reg_list[ARMV7M_PRIMASK].value, 0, 32, 1);
- armv7m->core_cache->reg_list[ARMV7M_PRIMASK].dirty = 1;
- armv7m->core_cache->reg_list[ARMV7M_PRIMASK].valid = 1;
+ armv7m->core_cache->reg_list[ARMV7M_PRIMASK].dirty = true;
+ armv7m->core_cache->reg_list[ARMV7M_PRIMASK].valid = true;
/* Make sure we are in Thumb mode */
buf_set_u32(armv7m->core_cache->reg_list[ARMV7M_xPSR].value, 0, 32,
buf_get_u32(armv7m->core_cache->reg_list[ARMV7M_xPSR].value, 0,
32) | (1 << 24));
- armv7m->core_cache->reg_list[ARMV7M_xPSR].dirty = 1;
- armv7m->core_cache->reg_list[ARMV7M_xPSR].valid = 1;
+ armv7m->core_cache->reg_list[ARMV7M_xPSR].dirty = true;
+ armv7m->core_cache->reg_list[ARMV7M_xPSR].valid = true;
}
#endif
}
LOG_DEBUG("resume pc = 0x%08" PRIx32, resume_pc);
buf_set_u32(arm->pc->value, 0, 32, resume_pc);
- arm->pc->dirty = 1;
- arm->pc->valid = 1;
+ arm->pc->dirty = true;
+ arm->pc->valid = true;
/* restore dpm_mode at system halt */
arm_dpm_modeswitch(&armv7a->dpm, ARM_MODE_ANY);
/* REVISIT v7a setup should be in a v7a-specific routine */
armv7a_init_arch_info(target, armv7a);
- target_register_timer_callback(cortex_a_handle_target_request, 1, 1, target);
+ target_register_timer_callback(cortex_a_handle_target_request, 1,
+ TARGET_TIMER_TYPE_PERIODIC, target);
return ERROR_OK;
}
static int cortex_a_target_create(struct target *target, Jim_Interp *interp)
{
- struct cortex_a_common *cortex_a = calloc(1, sizeof(struct cortex_a_common));
- cortex_a->common_magic = CORTEX_A_COMMON_MAGIC;
+ struct cortex_a_common *cortex_a;
struct adiv5_private_config *pc;
if (target->private_config == NULL)
pc = (struct adiv5_private_config *)target->private_config;
+ cortex_a = calloc(1, sizeof(struct cortex_a_common));
+ if (cortex_a == NULL) {
+ LOG_ERROR("Out of memory");
+ return ERROR_FAIL;
+ }
+ cortex_a->common_magic = CORTEX_A_COMMON_MAGIC;
cortex_a->armv7a_common.is_armv7r = false;
-
cortex_a->armv7a_common.arm.arm_vfp_version = ARM_VFP_V3;
return cortex_a_init_arch_info(target, cortex_a, pc->dap);
static int cortex_r4_target_create(struct target *target, Jim_Interp *interp)
{
- struct cortex_a_common *cortex_a = calloc(1, sizeof(struct cortex_a_common));
- cortex_a->common_magic = CORTEX_A_COMMON_MAGIC;
+ struct cortex_a_common *cortex_a;
struct adiv5_private_config *pc;
pc = (struct adiv5_private_config *)target->private_config;
if (adiv5_verify_config(pc) != ERROR_OK)
return ERROR_FAIL;
+ cortex_a = calloc(1, sizeof(struct cortex_a_common));
+ if (cortex_a == NULL) {
+ LOG_ERROR("Out of memory");
+ return ERROR_FAIL;
+ }
+ cortex_a->common_magic = CORTEX_A_COMMON_MAGIC;
cortex_a->armv7a_common.is_armv7r = true;
return cortex_a_init_arch_info(target, cortex_a, pc->dap);
static void cortex_a_deinit_target(struct target *target)
{
struct cortex_a_common *cortex_a = target_to_cortex_a(target);
- struct arm_dpm *dpm = &cortex_a->armv7a_common.dpm;
+ struct armv7a_common *armv7a = &cortex_a->armv7a_common;
+ struct arm_dpm *dpm = &armv7a->dpm;
+ uint32_t dscr;
+ int retval;
+
+ if (target_was_examined(target)) {
+ /* Disable halt for breakpoint, watchpoint and vector catch */
+ retval = mem_ap_read_atomic_u32(armv7a->debug_ap,
+ armv7a->debug_base + CPUDBG_DSCR, &dscr);
+ if (retval == ERROR_OK)
+ mem_ap_write_atomic_u32(armv7a->debug_ap,
+ armv7a->debug_base + CPUDBG_DSCR,
+ dscr & ~DSCR_HALT_DBG_MODE);
+ }
free(cortex_a->brp_list);
free(dpm->dbp);
return cortex_a_init_debug_access(target);
}
-COMMAND_HANDLER(cortex_a_handle_smp_off_command)
-{
- struct target *target = get_current_target(CMD_CTX);
- /* check target is an smp target */
- struct target_list *head;
- struct target *curr;
- head = target->head;
- target->smp = 0;
- if (head != (struct target_list *)NULL) {
- while (head != (struct target_list *)NULL) {
- curr = head->target;
- curr->smp = 0;
- head = head->next;
- }
- /* fixes the target display to the debugger */
- target->gdb_service->target = target;
- }
- return ERROR_OK;
-}
-
-COMMAND_HANDLER(cortex_a_handle_smp_on_command)
-{
- struct target *target = get_current_target(CMD_CTX);
- struct target_list *head;
- struct target *curr;
- head = target->head;
- if (head != (struct target_list *)NULL) {
- target->smp = 1;
- while (head != (struct target_list *)NULL) {
- curr = head->target;
- curr->smp = 1;
- head = head->next;
- }
- }
- return ERROR_OK;
-}
COMMAND_HANDLER(cortex_a_handle_smp_gdb_command)
{
.help = "Initialize core debug",
.usage = "",
},
- { .name = "smp_off",
- .handler = cortex_a_handle_smp_off_command,
- .mode = COMMAND_EXEC,
- .help = "Stop smp handling",
- .usage = "",},
- {
- .name = "smp_on",
- .handler = cortex_a_handle_smp_on_command,
- .mode = COMMAND_EXEC,
- .help = "Restart smp handling",
- .usage = "",
- },
{
.name = "smp_gdb",
.handler = cortex_a_handle_smp_gdb_command,
{
.chain = armv7a_mmu_command_handlers,
},
+ {
+ .chain = smp_command_handlers,
+ },
COMMAND_REGISTRATION_DONE
};
.deassert_reset = cortex_a_deassert_reset,
/* REVISIT allow exporting VFP3 registers ... */
+ .get_gdb_arch = arm_get_gdb_arch,
.get_gdb_reg_list = arm_get_gdb_reg_list,
.read_memory = cortex_a_read_memory,
.deassert_reset = cortex_a_deassert_reset,
/* REVISIT allow exporting VFP3 registers ... */
+ .get_gdb_arch = arm_get_gdb_arch,
.get_gdb_reg_list = arm_get_gdb_reg_list,
.read_memory = cortex_a_read_phys_memory,