+ if (dscr & DSCR_DTRRX_FULL_LATCHED) {
+ retval = cortex_a_exec_opcode(target, ARMV4_5_MRC(14, 0, 1, 0, 5, 0), &dscr);
+ if (final_retval == ERROR_OK)
+ final_retval = retval;
+ }
+
+ /* Done. */
+ return final_retval;
+}
+
+
+/*
+ * Cortex-A Memory access
+ *
+ * This is same Cortex-M3 but we must also use the correct
+ * ap number for every access.
+ */
+
+static int cortex_a_read_phys_memory(struct target *target,
+ target_addr_t address, uint32_t size,
+ uint32_t count, uint8_t *buffer)
+{
+ int retval;
+
+ if (!count || !buffer)
+ return ERROR_COMMAND_SYNTAX_ERROR;
+
+ LOG_DEBUG("Reading memory at real address " TARGET_ADDR_FMT "; size %" PRId32 "; count %" PRId32,
+ address, size, count);
+
+ /* read memory through the CPU */
+ cortex_a_prep_memaccess(target, 1);
+ retval = cortex_a_read_cpu_memory(target, address, size, count, buffer);
+ cortex_a_post_memaccess(target, 1);
+
+ return retval;
+}
+
+static int cortex_a_read_memory(struct target *target, target_addr_t address,
+ uint32_t size, uint32_t count, uint8_t *buffer)
+{
+ int retval;
+
+ /* cortex_a handles unaligned memory access */
+ LOG_DEBUG("Reading memory at address " TARGET_ADDR_FMT "; size %" PRId32 "; count %" PRId32,
+ address, size, count);
+
+ cortex_a_prep_memaccess(target, 0);
+ retval = cortex_a_read_cpu_memory(target, address, size, count, buffer);
+ cortex_a_post_memaccess(target, 0);
+
+ return retval;
+}
+
+static int cortex_a_write_phys_memory(struct target *target,
+ target_addr_t address, uint32_t size,
+ uint32_t count, const uint8_t *buffer)
+{
+ int retval;
+
+ if (!count || !buffer)
+ return ERROR_COMMAND_SYNTAX_ERROR;
+
+ LOG_DEBUG("Writing memory to real address " TARGET_ADDR_FMT "; size %" PRId32 "; count %" PRId32,
+ address, size, count);
+
+ /* write memory through the CPU */
+ cortex_a_prep_memaccess(target, 1);
+ retval = cortex_a_write_cpu_memory(target, address, size, count, buffer);
+ cortex_a_post_memaccess(target, 1);