coding style: add parenthesis around the argument of sizeof

[openocd.git] / src / target / armv8_dpm.c

diff --git a/src/target/armv8_dpm.c b/src/target/armv8_dpm.c
index 3c941fa2db17b97f09683dcdaee1c9675d4a164d..a3edb7f4752cd265dd01f63b1fbd6ea5a06c3ccb 100644 (file)
--- a/src/target/armv8_dpm.c
+++ b/src/target/armv8_dpm.c
@@ -573,6 +573,7 @@ int armv8_dpm_modeswitch(struct arm_dpm *dpm, enum arm_mode mode)
        case ARM_MODE_ABT:
        case ARM_MODE_IRQ:
        case ARM_MODE_FIQ:
+       case ARM_MODE_SYS:
                target_el = 1;
                break;
        /*
@@ -680,6 +681,10 @@ static int dpmv8_read_reg(struct arm_dpm *dpm, struct reg *r, unsigned regnum)
                        LOG_DEBUG("READ: %s, hvalue=%16.8llx", r->name, (unsigned long long) hvalue);
                }
        }
+
+       if (retval != ERROR_OK)
+               LOG_ERROR("Failed to read %s register", r->name);
+
        return retval;
 }
 
@@ -719,6 +724,9 @@ static int dpmv8_write_reg(struct arm_dpm *dpm, struct reg *r, unsigned regnum)
                }
        }
 
+       if (retval != ERROR_OK)
+               LOG_ERROR("Failed to write %s register", r->name);
+
        return retval;
 }
 
@@ -790,6 +798,10 @@ int armv8_dpm_read_current_registers(struct arm_dpm *dpm)
                                dpm->last_el != armv8_curel_from_core_mode(arm_reg->mode))
                        continue;
 
+               /* Special case: ARM_MODE_SYS has no SPSR at EL1 */
+               if (r->number == ARMV8_SPSR_EL1 && arm->core_mode == ARM_MODE_SYS)
+                       continue;
+
                retval = dpmv8_read_reg(dpm, r, i);
                if (retval != ERROR_OK)
                        goto fail;
@@ -1376,13 +1388,15 @@ void armv8_dpm_report_dscr(struct arm_dpm *dpm, uint32_t dscr)
                case DSCRV8_ENTRY_BKPT: /* SW BKPT (?) */
                case DSCRV8_ENTRY_RESET_CATCH:  /* Reset catch */
                case DSCRV8_ENTRY_OS_UNLOCK:  /*OS unlock catch*/
-               case DSCRV8_ENTRY_EXCEPTION_CATCH:  /*exception catch*/
                case DSCRV8_ENTRY_SW_ACCESS_DBG: /*SW access dbg register*/
                        target->debug_reason = DBG_REASON_BREAKPOINT;
                        break;
                case DSCRV8_ENTRY_WATCHPOINT:   /* asynch watchpoint */
                        target->debug_reason = DBG_REASON_WATCHPOINT;
                        break;
+               case DSCRV8_ENTRY_EXCEPTION_CATCH:  /*exception catch*/
+                       target->debug_reason = DBG_REASON_EXC_CATCH;
+                       break;
                default:
                        target->debug_reason = DBG_REASON_UNDEFINED;
                        break;
@@ -1457,10 +1471,10 @@ int armv8_dpm_setup(struct arm_dpm *dpm)
        /* FIXME add vector catch support */
 
        dpm->nbp = 1 + ((dpm->didr >> 12) & 0xf);
-       dpm->dbp = calloc(dpm->nbp, sizeof *dpm->dbp);
+       dpm->dbp = calloc(dpm->nbp, sizeof(*dpm->dbp));
 
        dpm->nwp = 1 + ((dpm->didr >> 20) & 0xf);
-       dpm->dwp = calloc(dpm->nwp, sizeof *dpm->dwp);
+       dpm->dwp = calloc(dpm->nwp, sizeof(*dpm->dwp));
 
        if (!dpm->dbp || !dpm->dwp) {
                free(dpm->dbp);