struct armv8_mmu_common {
/* following field mmu working way */
int32_t ttbr1_used; /* -1 not initialized, 0 no ttbr1 1 ttbr1 used and */
- uint32_t ttbr0_mask;/* masked to be used */
+ uint64_t ttbr0_mask;/* masked to be used */
uint32_t os_border;
int (*read_physical_memory)(struct target *target, target_addr_t address,
/* Core Debug Unit */
struct arm_dpm dpm;
uint32_t debug_base;
+ uint32_t cti_base;
+
struct adiv5_ap *debug_ap;
struct adiv5_ap *memory_ap;
bool memory_ap_available;
uint8_t cpu_id;
bool is_armv7r;
+ /* armv8 aarch64 need below information for page translation */
+ uint8_t va_size;
+ uint8_t pa_size;
+ uint32_t page_size;
+ uint64_t ttbr_base;
+
/* cache specific to V7 Memory Management Unit compatible with v4_5*/
struct armv8_mmu_common armv8_mmu;
#define CPUV8_DBG_AUTHSTATUS 0xFB8
+/*define CTI(cross trigger interface)*/
+#define CTI_CTR 0x0
+#define CTI_INACK 0x10
+#define CTI_APPSET 0x14
+#define CTI_APPCLEAR 0x18
+#define CTI_APPPULSE 0x1C
+#define CTI_INEN0 0x20
+#define CTI_INEN1 0x24
+#define CTI_INEN2 0x28
+#define CTI_INEN3 0x2C
+#define CTI_INEN4 0x30
+#define CTI_INEN5 0x34
+#define CTI_INEN6 0x38
+#define CTI_INEN7 0x3C
+#define CTI_OUTEN0 0xA0
+#define CTI_OUTEN1 0xA4
+#define CTI_OUTEN2 0xA8
+#define CTI_OUTEN3 0xAC
+#define CTI_OUTEN4 0xB0
+#define CTI_OUTEN5 0xB4
+#define CTI_OUTEN6 0xB8
+#define CTI_OUTEN7 0xBC
+#define CTI_TRIN_STATUS 0x130
+#define CTI_TROUT_STATUS 0x134
+#define CTI_CHIN_STATUS 0x138
+#define CTI_CHOU_STATUS 0x13C
+#define CTI_GATE 0x140
+#define CTI_UNLOCK 0xFB0
+
+#define PAGE_SIZE_4KB 0x1000
+#define PAGE_SIZE_4KB_LEVEL0_BITS 39
+#define PAGE_SIZE_4KB_LEVEL1_BITS 30
+#define PAGE_SIZE_4KB_LEVEL2_BITS 21
+#define PAGE_SIZE_4KB_LEVEL3_BITS 12
+
+#define PAGE_SIZE_4KB_LEVEL0_MASK ((0x1FFULL) << PAGE_SIZE_4KB_LEVEL0_BITS)
+#define PAGE_SIZE_4KB_LEVEL1_MASK ((0x1FFULL) << PAGE_SIZE_4KB_LEVEL1_BITS)
+#define PAGE_SIZE_4KB_LEVEL2_MASK ((0x1FFULL) << PAGE_SIZE_4KB_LEVEL2_BITS)
+#define PAGE_SIZE_4KB_LEVEL3_MASK ((0x1FFULL) << PAGE_SIZE_4KB_LEVEL3_BITS)
+
+#define PAGE_SIZE_4KB_TRBBASE_MASK 0xFFFFFFFFF000
int armv8_arch_state(struct target *target);
int armv8_identify_cache(struct target *target);