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aarch64: add basic Aarch32 support
[openocd.git] / src / target / armv8.c
diff --git a/src/target/armv8.c b/src/target/armv8.c
index e516518ad4faf5f8eb23cfe21c13991eb9253845..306a06e7a0b14ef5cc27ee7e93e81e62a8b4a93b 100644 (file)
--- a/src/target/armv8.c
+++ b/src/target/armv8.c
@@ -34,10 +34,132 @@
 #include <unistd.h>
 
 #include "armv8_opcodes.h"
 #include <unistd.h>
 
 #include "armv8_opcodes.h"
-#include "arm_opcodes.h"
 #include "target.h"
 #include "target_type.h"
 
 #include "target.h"
 #include "target_type.h"
 
+static const char * const armv8_state_strings[] = {
+       "AArch32", "Thumb", "Jazelle", "ThumbEE", "AArch64",
+};
+
+static const struct {
+       const char *name;
+       unsigned psr;
+       /* For user and system modes, these list indices for all registers.
+        * otherwise they're just indices for the shadow registers and SPSR.
+        */
+       unsigned short n_indices;
+       const uint8_t *indices;
+} armv8_mode_data[] = {
+       /* These special modes are currently only supported
+        * by ARMv6M and ARMv7M profiles */
+       {
+               .name = "USR",
+               .psr = ARM_MODE_USR,
+       },
+       {
+               .name = "FIQ",
+               .psr = ARM_MODE_FIQ,
+       },
+       {
+               .name = "IRQ",
+               .psr = ARM_MODE_IRQ,
+       },
+       {
+               .name = "SVC",
+               .psr = ARM_MODE_SVC,
+       },
+       {
+               .name = "MON",
+               .psr = ARM_MODE_MON,
+       },
+       {
+               .name = "ABT",
+               .psr = ARM_MODE_ABT,
+       },
+       {
+               .name = "EL0T",
+               .psr = ARMV8_64_EL0T,
+       },
+       {
+               .name = "EL1T",
+               .psr = ARMV8_64_EL1T,
+       },
+       {
+               .name = "EL1H",
+               .psr = ARMV8_64_EL1H,
+       },
+       {
+               .name = "EL2T",
+               .psr = ARMV8_64_EL2T,
+       },
+       {
+               .name = "EL2H",
+               .psr = ARMV8_64_EL2H,
+       },
+       {
+               .name = "EL3T",
+               .psr = ARMV8_64_EL3T,
+       },
+       {
+               .name = "EL3H",
+               .psr = ARMV8_64_EL3H,
+       },
+};
+
+/** Map PSR mode bits to the name of an ARM processor operating mode. */
+const char *armv8_mode_name(unsigned psr_mode)
+{
+       for (unsigned i = 0; i < ARRAY_SIZE(armv8_mode_data); i++) {
+               if (armv8_mode_data[i].psr == psr_mode)
+                       return armv8_mode_data[i].name;
+       }
+       LOG_ERROR("unrecognized psr mode: %#02x", psr_mode);
+       return "UNRECOGNIZED";
+}
+
+int armv8_mode_to_number(enum arm_mode mode)
+{
+       switch (mode) {
+               case ARM_MODE_ANY:
+               /* map MODE_ANY to user mode */
+               case ARM_MODE_USR:
+                       return 0;
+               case ARM_MODE_FIQ:
+                       return 1;
+               case ARM_MODE_IRQ:
+                       return 2;
+               case ARM_MODE_SVC:
+                       return 3;
+               case ARM_MODE_ABT:
+                       return 4;
+               case ARM_MODE_UND:
+                       return 5;
+               case ARM_MODE_SYS:
+                       return 6;
+               case ARM_MODE_MON:
+                       return 7;
+               case ARMV8_64_EL0T:
+                       return 8;
+               case ARMV8_64_EL1T:
+                       return 9;
+               case ARMV8_64_EL1H:
+                       return 10;
+               case ARMV8_64_EL2T:
+                       return 11;
+               case ARMV8_64_EL2H:
+                       return 12;
+               case ARMV8_64_EL3T:
+                       return 13;
+               case ARMV8_64_EL3H:
+                       return 14;
+
+               default:
+                       LOG_ERROR("invalid mode value encountered %d", mode);
+                       return -1;
+       }
+}
+
+
 static int armv8_read_core_reg(struct target *target, struct reg *r,
        int num, enum arm_mode mode)
 {
 static int armv8_read_core_reg(struct target *target, struct reg *r,
        int num, enum arm_mode mode)
 {
@@ -86,37 +208,284 @@ static int armv8_write_core_reg(struct target *target, struct reg *r,
        return ERROR_OK;
 }
 #endif
        return ERROR_OK;
 }
 #endif
+/**
+ * Configures host-side ARM records to reflect the specified CPSR.
+ * Later, code can use arm_reg_current() to map register numbers
+ * according to how they are exposed by this mode.
+ */
+void armv8_set_cpsr(struct arm *arm, uint32_t cpsr)
+{
+       uint32_t mode = cpsr & 0x1F;
+
+       /* NOTE:  this may be called very early, before the register
+        * cache is set up.  We can't defend against many errors, in
+        * particular against CPSRs that aren't valid *here* ...
+        */
+       if (arm->cpsr) {
+               buf_set_u32(arm->cpsr->value, 0, 32, cpsr);
+               arm->cpsr->valid = 1;
+               arm->cpsr->dirty = 0;
+       }
+
+       /* Older ARMs won't have the J bit */
+       enum arm_state state = 0xFF;
+
+       if (((cpsr & 0x10) >> 4) == 0) {
+               state = ARM_STATE_AARCH64;
+       } else {
+               if (cpsr & (1 << 5)) {  /* T */
+                       if (cpsr & (1 << 24)) { /* J */
+                               LOG_WARNING("ThumbEE -- incomplete support");
+                               state = ARM_STATE_THUMB_EE;
+                       } else
+                               state = ARM_STATE_THUMB;
+               } else {
+                       if (cpsr & (1 << 24)) { /* J */
+                               LOG_ERROR("Jazelle state handling is BROKEN!");
+                               state = ARM_STATE_JAZELLE;
+                       } else
+                               state = ARM_STATE_ARM;
+               }
+       }
+       arm->core_state = state;
+       if (arm->core_state == ARM_STATE_AARCH64) {
+               switch (mode) {
+                       case SYSTEM_AAR64_MODE_EL0t:
+                               arm->core_mode = ARMV8_64_EL0T;
+                       break;
+                       case SYSTEM_AAR64_MODE_EL1t:
+                               arm->core_mode = ARMV8_64_EL0T;
+                       break;
+                       case SYSTEM_AAR64_MODE_EL1h:
+                               arm->core_mode = ARMV8_64_EL1H;
+                       break;
+                       case SYSTEM_AAR64_MODE_EL2t:
+                               arm->core_mode = ARMV8_64_EL2T;
+                       break;
+                       case SYSTEM_AAR64_MODE_EL2h:
+                               arm->core_mode = ARMV8_64_EL2H;
+                       break;
+                       case SYSTEM_AAR64_MODE_EL3t:
+                               arm->core_mode = ARMV8_64_EL3T;
+                       break;
+                       case SYSTEM_AAR64_MODE_EL3h:
+                               arm->core_mode = ARMV8_64_EL3H;
+                       break;
+                       default:
+                               LOG_DEBUG("unknow mode 0x%x", (unsigned) (mode));
+                       break;
+               }
+       } else {
+               arm->core_mode = mode;
+       }
+
+       LOG_DEBUG("set CPSR %#8.8x: %s mode, %s state", (unsigned) cpsr,
+               armv8_mode_name(arm->core_mode),
+               armv8_state_strings[arm->core_state]);
+}
+
+static void armv8_show_fault_registers32(struct armv8_common *armv8)
+{
+       uint32_t dfsr, ifsr, dfar, ifar;
+       struct arm_dpm *dpm = armv8->arm.dpm;
+       int retval;
+
+       retval = dpm->prepare(dpm);
+       if (retval != ERROR_OK)
+               return;
+
+       /* ARMV4_5_MRC(cpnum, op1, r0, CRn, CRm, op2) */
+
+       /* c5/c0 - {data, instruction} fault status registers */
+       retval = dpm->instr_read_data_r0(dpm,
+                       T32_FMTITR(ARMV4_5_MRC(15, 0, 0, 5, 0, 0)),
+                       &dfsr);
+       if (retval != ERROR_OK)
+               goto done;
+
+       retval = dpm->instr_read_data_r0(dpm,
+                       T32_FMTITR(ARMV4_5_MRC(15, 0, 0, 5, 0, 1)),
+                       &ifsr);
+       if (retval != ERROR_OK)
+               goto done;
+
+       /* c6/c0 - {data, instruction} fault address registers */
+       retval = dpm->instr_read_data_r0(dpm,
+                       T32_FMTITR(ARMV4_5_MRC(15, 0, 0, 6, 0, 0)),
+                       &dfar);
+       if (retval != ERROR_OK)
+               goto done;
+
+       retval = dpm->instr_read_data_r0(dpm,
+                       T32_FMTITR(ARMV4_5_MRC(15, 0, 0, 6, 0, 2)),
+                       &ifar);
+       if (retval != ERROR_OK)
+               goto done;
+
+       LOG_USER("Data fault registers        DFSR: %8.8" PRIx32
+               ", DFAR: %8.8" PRIx32, dfsr, dfar);
+       LOG_USER("Instruction fault registers IFSR: %8.8" PRIx32
+               ", IFAR: %8.8" PRIx32, ifsr, ifar);
+
+done:
+       /* (void) */ dpm->finish(dpm);
+}
 
 static void armv8_show_fault_registers(struct target *target)
 {
 
 static void armv8_show_fault_registers(struct target *target)
 {
-       /* TODO */
+       struct armv8_common *armv8 = target_to_armv8(target);
+
+       if (armv8->arm.core_state != ARM_STATE_AARCH64)
+               armv8_show_fault_registers32(armv8);
 }
 
 }
 
-static int armv8_read_ttbcr(struct target *target)
+static uint8_t armv8_pa_size(uint32_t ps)
+{
+       uint8_t ret = 0;
+       switch (ps) {
+               case 0:
+                       ret = 32;
+                       break;
+               case 1:
+                       ret = 36;
+                       break;
+               case 2:
+                       ret = 40;
+                       break;
+               case 3:
+                       ret = 42;
+                       break;
+               case 4:
+                       ret = 44;
+                       break;
+               case 5:
+                       ret = 48;
+                       break;
+               default:
+                       LOG_INFO("Unknow physicall address size");
+                       break;
+       }
+       return ret;
+}
+
+static int armv8_read_ttbcr32(struct target *target)
 {
        struct armv8_common *armv8 = target_to_armv8(target);
        struct arm_dpm *dpm = armv8->arm.dpm;
 {
        struct armv8_common *armv8 = target_to_armv8(target);
        struct arm_dpm *dpm = armv8->arm.dpm;
-       uint32_t ttbcr;
+       uint32_t ttbcr, ttbcr_n;
        int retval = dpm->prepare(dpm);
        if (retval != ERROR_OK)
                goto done;
        /*  MRC p15,0,<Rt>,c2,c0,2 ; Read CP15 Translation Table Base Control Register*/
        retval = dpm->instr_read_data_r0(dpm,
        int retval = dpm->prepare(dpm);
        if (retval != ERROR_OK)
                goto done;
        /*  MRC p15,0,<Rt>,c2,c0,2 ; Read CP15 Translation Table Base Control Register*/
        retval = dpm->instr_read_data_r0(dpm,
-                       ARMV4_5_MRC(15, 0, 0, 2, 0, 2),
+                       T32_FMTITR(ARMV4_5_MRC(15, 0, 0, 2, 0, 2)),
                        &ttbcr);
        if (retval != ERROR_OK)
                goto done;
                        &ttbcr);
        if (retval != ERROR_OK)
                goto done;
-       armv8->armv8_mmu.ttbr1_used = ((ttbcr & 0x7) != 0) ? 1 : 0;
-       armv8->armv8_mmu.ttbr0_mask  = 7 << (32 - ((ttbcr & 0x7)));
+
+       LOG_DEBUG("ttbcr %" PRIx32, ttbcr);
+
+       ttbcr_n = ttbcr & 0x7;
+       armv8->armv8_mmu.ttbcr = ttbcr;
+
+       /*
+        * ARM Architecture Reference Manual (ARMv7-A and ARMv7-Redition),
+        * document # ARM DDI 0406C
+        */
+       armv8->armv8_mmu.ttbr_range[0]  = 0xffffffff >> ttbcr_n;
+       armv8->armv8_mmu.ttbr_range[1] = 0xffffffff;
+       armv8->armv8_mmu.ttbr_mask[0] = 0xffffffff << (14 - ttbcr_n);
+       armv8->armv8_mmu.ttbr_mask[1] = 0xffffffff << 14;
+
+       LOG_DEBUG("ttbr1 %s, ttbr0_mask %" PRIx32 " ttbr1_mask %" PRIx32,
+                 (ttbcr_n != 0) ? "used" : "not used",
+                 armv8->armv8_mmu.ttbr_mask[0],
+                 armv8->armv8_mmu.ttbr_mask[1]);
+
+done:
+       dpm->finish(dpm);
+       return retval;
+}
+
+static int armv8_read_ttbcr(struct target *target)
+{
+       struct armv8_common *armv8 = target_to_armv8(target);
+       struct arm_dpm *dpm = armv8->arm.dpm;
+       struct arm *arm = &armv8->arm;
+       uint32_t ttbcr;
+       uint64_t ttbcr_64;
+
+       int retval = dpm->prepare(dpm);
+       if (retval != ERROR_OK)
+               goto done;
+
+       /* claaer ttrr1_used and ttbr0_mask */
+       memset(&armv8->armv8_mmu.ttbr1_used, 0, sizeof(armv8->armv8_mmu.ttbr1_used));
+       memset(&armv8->armv8_mmu.ttbr0_mask, 0, sizeof(armv8->armv8_mmu.ttbr0_mask));
+
+       switch (arm->core_mode) {
+               case ARMV8_64_EL3H:
+               case ARMV8_64_EL3T:
+                       retval = dpm->instr_read_data_r0(dpm,
+                                       ARMV8_MRS(SYSTEM_TCR_EL3, 0),
+                                       &ttbcr);
+                       retval += dpm->instr_read_data_r0_64(dpm,
+                                       ARMV8_MRS(SYSTEM_TTBR0_EL3, 0),
+                                       &armv8->ttbr_base);
+                       if (retval != ERROR_OK)
+                               goto done;
+                       armv8->va_size = 64 - (ttbcr & 0x3F);
+                       armv8->pa_size = armv8_pa_size((ttbcr >> 16) & 7);
+                       armv8->page_size = (ttbcr >> 14) & 3;
+                       break;
+               case ARMV8_64_EL2T:
+               case ARMV8_64_EL2H:
+                       retval = dpm->instr_read_data_r0(dpm,
+                                       ARMV8_MRS(SYSTEM_TCR_EL2, 0),
+                                       &ttbcr);
+                       retval += dpm->instr_read_data_r0_64(dpm,
+                                       ARMV8_MRS(SYSTEM_TTBR0_EL2, 0),
+                                       &armv8->ttbr_base);
+                       if (retval != ERROR_OK)
+                               goto done;
+                       armv8->va_size = 64 - (ttbcr & 0x3F);
+                       armv8->pa_size = armv8_pa_size((ttbcr >> 16) & 7);
+                       armv8->page_size = (ttbcr >> 14) & 3;
+                       break;
+               case ARMV8_64_EL0T:
+               case ARMV8_64_EL1T:
+               case ARMV8_64_EL1H:
+                       retval = dpm->instr_read_data_r0_64(dpm,
+                                       ARMV8_MRS(SYSTEM_TCR_EL1, 0),
+                                       &ttbcr_64);
+                       armv8->va_size = 64 - (ttbcr_64 & 0x3F);
+                       armv8->pa_size = armv8_pa_size((ttbcr_64 >> 32) & 7);
+                       armv8->page_size = (ttbcr_64 >> 14) & 3;
+                       armv8->armv8_mmu.ttbr1_used = (((ttbcr_64 >> 16) & 0x3F) != 0) ? 1 : 0;
+                       armv8->armv8_mmu.ttbr0_mask  = 0x0000FFFFFFFFFFFF;
+                       retval += dpm->instr_read_data_r0_64(dpm,
+                                       ARMV8_MRS(SYSTEM_TTBR0_EL1 | (armv8->armv8_mmu.ttbr1_used), 0),
+                                       &armv8->ttbr_base);
+                       if (retval != ERROR_OK)
+                               goto done;
+                       break;
+               default:
+                       LOG_ERROR("unknow core state");
+                       retval = ERROR_FAIL;
+                       break;
+       }
+       if (retval != ERROR_OK)
+               goto done;
+
 #if 0
 #if 0
-       LOG_INFO("ttb1 %s ,ttb0_mask %x",
+       LOG_INFO("ttb1 %s ,ttb0_mask %llx",
                armv8->armv8_mmu.ttbr1_used ? "used" : "not used",
                armv8->armv8_mmu.ttbr0_mask);
 #endif
        if (armv8->armv8_mmu.ttbr1_used == 1) {
                armv8->armv8_mmu.ttbr1_used ? "used" : "not used",
                armv8->armv8_mmu.ttbr0_mask);
 #endif
        if (armv8->armv8_mmu.ttbr1_used == 1) {
-               LOG_INFO("SVC access above %" PRIx32,
-                        (uint32_t)(0xffffffff & armv8->armv8_mmu.ttbr0_mask));
-               armv8->armv8_mmu.os_border = 0xffffffff & armv8->armv8_mmu.ttbr0_mask;
+               LOG_INFO("TTBR0 access above %" PRIx64,
+                        (uint64_t)(armv8->armv8_mmu.ttbr0_mask));
+               armv8->armv8_mmu.os_border = armv8->armv8_mmu.ttbr0_mask;
        } else {
                /*  fix me , default is hard coded LINUX border  */
                armv8->armv8_mmu.os_border = 0xc0000000;
        } else {
                /*  fix me , default is hard coded LINUX border  */
                armv8->armv8_mmu.os_border = 0xc0000000;
@@ -126,104 +495,30 @@ done:
        return retval;
 }
 
        return retval;
 }
 
+static int armv8_4K_translate(struct target *target,  target_addr_t va, target_addr_t *val)
+{
+       LOG_ERROR("4K page Address translation need to add");
+       return ERROR_FAIL;
+}
+
 
 /*  method adapted to cortex A : reused arm v4 v5 method*/
 
 /*  method adapted to cortex A : reused arm v4 v5 method*/
-int armv8_mmu_translate_va(struct target *target,  uint32_t va, uint32_t *val)
+int armv8_mmu_translate_va(struct target *target,  target_addr_t va, target_addr_t *val)
 {
 {
-       uint32_t first_lvl_descriptor = 0x0;
-       uint32_t second_lvl_descriptor = 0x0;
-       int retval;
+       int retval = ERROR_FAIL;
        struct armv8_common *armv8 = target_to_armv8(target);
        struct arm_dpm *dpm = armv8->arm.dpm;
        struct armv8_common *armv8 = target_to_armv8(target);
        struct arm_dpm *dpm = armv8->arm.dpm;
-       uint32_t ttb = 0;       /*  default ttb0 */
-       if (armv8->armv8_mmu.ttbr1_used == -1)
-               armv8_read_ttbcr(target);
-       if ((armv8->armv8_mmu.ttbr1_used) &&
-               (va > (0xffffffff & armv8->armv8_mmu.ttbr0_mask))) {
-               /*  select ttb 1 */
-               ttb = 1;
-       }
+
        retval = dpm->prepare(dpm);
        retval = dpm->prepare(dpm);
+       retval += armv8_read_ttbcr(target);
        if (retval != ERROR_OK)
                goto done;
        if (retval != ERROR_OK)
                goto done;
-
-       /*  MRC p15,0,<Rt>,c2,c0,ttb */
-       retval = dpm->instr_read_data_r0(dpm,
-                       ARMV4_5_MRC(15, 0, 0, 2, 0, ttb),
-                       &ttb);
-       if (retval != ERROR_OK)
-               return retval;
-       retval = armv8->armv8_mmu.read_physical_memory(target,
-                       (ttb & 0xffffc000) | ((va & 0xfff00000) >> 18),
-                       4, 1, (uint8_t *)&first_lvl_descriptor);
-       if (retval != ERROR_OK)
-               return retval;
-       first_lvl_descriptor = target_buffer_get_u32(target, (uint8_t *)
-                       &first_lvl_descriptor);
-       /*  reuse armv4_5 piece of code, specific armv8 changes may come later */
-       LOG_DEBUG("1st lvl desc: %8.8" PRIx32 "", first_lvl_descriptor);
-
-       if ((first_lvl_descriptor & 0x3) == 0) {
-               LOG_ERROR("Address translation failure");
-               return ERROR_TARGET_TRANSLATION_FAULT;
-       }
-
-
-       if ((first_lvl_descriptor & 0x3) == 2) {
-               /* section descriptor */
-               *val = (first_lvl_descriptor & 0xfff00000) | (va & 0x000fffff);
-               return ERROR_OK;
-       }
-
-       if ((first_lvl_descriptor & 0x3) == 1) {
-               /* coarse page table */
-               retval = armv8->armv8_mmu.read_physical_memory(target,
-                               (first_lvl_descriptor & 0xfffffc00) | ((va & 0x000ff000) >> 10),
-                               4, 1, (uint8_t *)&second_lvl_descriptor);
-               if (retval != ERROR_OK)
-                       return retval;
-       } else if ((first_lvl_descriptor & 0x3) == 3)   {
-               /* fine page table */
-               retval = armv8->armv8_mmu.read_physical_memory(target,
-                               (first_lvl_descriptor & 0xfffff000) | ((va & 0x000ffc00) >> 8),
-                               4, 1, (uint8_t *)&second_lvl_descriptor);
-               if (retval != ERROR_OK)
-                       return retval;
-       }
-
-       second_lvl_descriptor = target_buffer_get_u32(target, (uint8_t *)
-                       &second_lvl_descriptor);
-
-       LOG_DEBUG("2nd lvl desc: %8.8" PRIx32 "", second_lvl_descriptor);
-
-       if ((second_lvl_descriptor & 0x3) == 0) {
-               LOG_ERROR("Address translation failure");
-               return ERROR_TARGET_TRANSLATION_FAULT;
-       }
-
-       if ((second_lvl_descriptor & 0x3) == 1) {
-               /* large page descriptor */
-               *val = (second_lvl_descriptor & 0xffff0000) | (va & 0x0000ffff);
-               return ERROR_OK;
-       }
-
-       if ((second_lvl_descriptor & 0x3) == 2) {
-               /* small page descriptor */
-               *val = (second_lvl_descriptor & 0xfffff000) | (va & 0x00000fff);
-               return ERROR_OK;
-       }
-
-       if ((second_lvl_descriptor & 0x3) == 3) {
-               *val = (second_lvl_descriptor & 0xfffffc00) | (va & 0x000003ff);
-               return ERROR_OK;
-       }
-
-       /* should not happen */
-       LOG_ERROR("Address translation failure");
-       return ERROR_TARGET_TRANSLATION_FAULT;
+       if (armv8->page_size == 0)
+               return armv8_4K_translate(target, va, val);
 
 done:
 
 done:
-       return retval;
+       dpm->finish(dpm);
+       return ERROR_FAIL;
 }
 
 /*  V8 method VA TO PA  */
 }
 
 /*  V8 method VA TO PA  */
@@ -282,7 +577,7 @@ static int _armv8_flush_all_data(struct target *target)
                        /*  DCCISW */
                        /* LOG_INFO ("%d %d %x",c_way,c_index,value); */
                        retval = dpm->instr_write_data_r0(dpm,
                        /*  DCCISW */
                        /* LOG_INFO ("%d %d %x",c_way,c_index,value); */
                        retval = dpm->instr_write_data_r0(dpm,
-                                       ARMV4_5_MCR(15, 0, 0, 7, 14, 2),
+                                       ARMV8_MSR_GP(SYSTEM_DCCISW, 0),
                                        value);
                        if (retval != ERROR_OK)
                                goto done;
                                        value);
                        if (retval != ERROR_OK)
                                goto done;
@@ -346,14 +641,13 @@ static int armv8_read_mpidr(struct target *target)
        struct armv8_common *armv8 = target_to_armv8(target);
        struct arm_dpm *dpm = armv8->arm.dpm;
        uint32_t mpidr;
        struct armv8_common *armv8 = target_to_armv8(target);
        struct arm_dpm *dpm = armv8->arm.dpm;
        uint32_t mpidr;
+
        retval = dpm->prepare(dpm);
        if (retval != ERROR_OK)
                goto done;
        /* MRC p15,0,<Rd>,c0,c0,5; read Multiprocessor ID register*/
 
        retval = dpm->prepare(dpm);
        if (retval != ERROR_OK)
                goto done;
        /* MRC p15,0,<Rd>,c0,c0,5; read Multiprocessor ID register*/
 
-       retval = dpm->instr_read_data_r0(dpm,
-                       ARMV8_MRS(SYSTEM_MPIDR, 0),
-                       &mpidr);
+       retval = dpm->instr_read_data_r0(dpm, armv8_opcode(armv8, READ_REG_MPIDR), &mpidr);
        if (retval != ERROR_OK)
                goto done;
        if (mpidr & 1<<31) {
        if (retval != ERROR_OK)
                goto done;
        if (mpidr & 1<<31) {
@@ -377,84 +671,65 @@ done:
 
 int armv8_identify_cache(struct target *target)
 {
 
 int armv8_identify_cache(struct target *target)
 {
-       /*  read cache descriptor */
+       /*      read cache descriptor */
        int retval = ERROR_FAIL;
        struct armv8_common *armv8 = target_to_armv8(target);
        struct arm_dpm *dpm = armv8->arm.dpm;
        uint32_t cache_selected, clidr;
        uint32_t cache_i_reg, cache_d_reg;
        struct armv8_cache_common *cache = &(armv8->armv8_mmu.armv8_cache);
        int retval = ERROR_FAIL;
        struct armv8_common *armv8 = target_to_armv8(target);
        struct arm_dpm *dpm = armv8->arm.dpm;
        uint32_t cache_selected, clidr;
        uint32_t cache_i_reg, cache_d_reg;
        struct armv8_cache_common *cache = &(armv8->armv8_mmu.armv8_cache);
-       if (!armv8->is_armv7r)
-               armv8_read_ttbcr(target);
-       retval = dpm->prepare(dpm);
+       int is_aarch64 = armv8->arm.core_state == ARM_STATE_AARCH64;
+
+       retval = is_aarch64 ? armv8_read_ttbcr(target) : armv8_read_ttbcr32(target);
+       if (retval != ERROR_OK)
+               return retval;
 
 
+       retval = dpm->prepare(dpm);
        if (retval != ERROR_OK)
                goto done;
        if (retval != ERROR_OK)
                goto done;
-       /*  retrieve CLIDR
-        *  mrc p15, 1, r0, c0, c0, 1           @ read clidr */
-       retval = dpm->instr_read_data_r0(dpm,
-                       ARMV4_5_MRC(15, 1, 0, 0, 0, 1),
-                       &clidr);
+
+       /*      retrieve CLIDR */
+       retval = dpm->instr_read_data_r0(dpm, armv8_opcode(armv8, READ_REG_CLIDR), &clidr);
        if (retval != ERROR_OK)
                goto done;
        if (retval != ERROR_OK)
                goto done;
+
        clidr = (clidr & 0x7000000) >> 23;
        LOG_INFO("number of cache level %" PRIx32, (uint32_t)(clidr / 2));
        if ((clidr / 2) > 1) {
                /* FIXME not supported present in cortex A8 and later */
        clidr = (clidr & 0x7000000) >> 23;
        LOG_INFO("number of cache level %" PRIx32, (uint32_t)(clidr / 2));
        if ((clidr / 2) > 1) {
                /* FIXME not supported present in cortex A8 and later */
-               /*  in cortex A7, A15 */
+               /*      in cortex A7, A15 */
                LOG_ERROR("cache l2 present :not supported");
        }
                LOG_ERROR("cache l2 present :not supported");
        }
-       /*  retrieve selected cache
-        *  MRC p15, 2,<Rd>, c0, c0, 0; Read CSSELR */
-       retval = dpm->instr_read_data_r0(dpm,
-                       ARMV4_5_MRC(15, 2, 0, 0, 0, 0),
-                       &cache_selected);
+       /*      retrieve selected cache*/
+       retval = dpm->instr_read_data_r0(dpm, armv8_opcode(armv8, READ_REG_CSSELR), &cache_selected);
        if (retval != ERROR_OK)
                goto done;
 
        if (retval != ERROR_OK)
                goto done;
 
-       retval = armv8->arm.mrc(target, 15,
-                       2, 0,   /* op1, op2 */
-                       0, 0,   /* CRn, CRm */
-                       &cache_selected);
-       if (retval != ERROR_OK)
-               goto done;
        /* select instruction cache
        /* select instruction cache
-        *  MCR p15, 2,<Rd>, c0, c0, 0; Write CSSELR
-        *  [0]  : 1 instruction cache selection , 0 data cache selection */
-       retval = dpm->instr_write_data_r0(dpm,
-                       ARMV4_5_MRC(15, 2, 0, 0, 0, 0),
-                       1);
+        *      [0]  : 1 instruction cache selection , 0 data cache selection */
+       retval = dpm->instr_write_data_r0(dpm, armv8_opcode(armv8, WRITE_REG_CSSELR), 1);
        if (retval != ERROR_OK)
                goto done;
 
        /* read CCSIDR
         * MRC P15,1,<RT>,C0, C0,0 ;on cortex A9 read CCSIDR
        if (retval != ERROR_OK)
                goto done;
 
        /* read CCSIDR
         * MRC P15,1,<RT>,C0, C0,0 ;on cortex A9 read CCSIDR
-        * [2:0] line size  001 eight word per line
+        * [2:0] line size      001 eight word per line
         * [27:13] NumSet 0x7f 16KB, 0xff 32Kbytes, 0x1ff 64Kbytes */
         * [27:13] NumSet 0x7f 16KB, 0xff 32Kbytes, 0x1ff 64Kbytes */
-       retval = dpm->instr_read_data_r0(dpm,
-                       ARMV4_5_MRC(15, 1, 0, 0, 0, 0),
-                       &cache_i_reg);
+       retval = dpm->instr_read_data_r0(dpm, armv8_opcode(armv8, READ_REG_CCSIDR), &cache_i_reg);
        if (retval != ERROR_OK)
                goto done;
 
        if (retval != ERROR_OK)
                goto done;
 
-       /*  select data cache*/
-       retval = dpm->instr_write_data_r0(dpm,
-                       ARMV4_5_MRC(15, 2, 0, 0, 0, 0),
-                       0);
+       /*      select data cache*/
+       retval = dpm->instr_write_data_r0(dpm, armv8_opcode(armv8, WRITE_REG_CSSELR), 0);
        if (retval != ERROR_OK)
                goto done;
 
        if (retval != ERROR_OK)
                goto done;
 
-       retval = dpm->instr_read_data_r0(dpm,
-                       ARMV4_5_MRC(15, 1, 0, 0, 0, 0),
-                       &cache_d_reg);
+       retval = dpm->instr_read_data_r0(dpm, armv8_opcode(armv8, READ_REG_CCSIDR), &cache_d_reg);
        if (retval != ERROR_OK)
                goto done;
 
        if (retval != ERROR_OK)
                goto done;
 
-       /*  restore selected cache  */
-       dpm->instr_write_data_r0(dpm,
-               ARMV4_5_MRC(15, 2, 0, 0, 0, 0),
-               cache_selected);
-
+       /*      restore selected cache  */
+       dpm->instr_write_data_r0(dpm, armv8_opcode(armv8, WRITE_REG_CSSELR), cache_selected);
        if (retval != ERROR_OK)
                goto done;
        dpm->finish(dpm);
        if (retval != ERROR_OK)
                goto done;
        dpm->finish(dpm);
@@ -549,6 +824,27 @@ int armv8_init_arch_info(struct target *target, struct armv8_common *armv8)
        return ERROR_OK;
 }
 
        return ERROR_OK;
 }
 
+int armv8_aarch64_state(struct target *target)
+{
+       struct arm *arm = target_to_arm(target);
+
+       if (arm->common_magic != ARM_COMMON_MAGIC) {
+               LOG_ERROR("BUG: called for a non-ARM target");
+               return ERROR_FAIL;
+       }
+
+       LOG_USER("target halted in %s state due to %s, current mode: %s\n"
+               "cpsr: 0x%8.8" PRIx32 " pc: 0x%" PRIx64 "%s",
+               armv8_state_strings[arm->core_state],
+               debug_reason_name(target),
+               armv8_mode_name(arm->core_mode),
+               buf_get_u32(arm->cpsr->value, 0, 32),
+               buf_get_u64(arm->pc->value, 0, 64),
+               arm->is_semihosting ? ", semihosting" : "");
+
+       return ERROR_OK;
+}
+
 int armv8_arch_state(struct target *target)
 {
        static const char * const state[] = {
 int armv8_arch_state(struct target *target)
 {
        static const char * const state[] = {
@@ -563,21 +859,19 @@ int armv8_arch_state(struct target *target)
                return ERROR_COMMAND_SYNTAX_ERROR;
        }
 
                return ERROR_COMMAND_SYNTAX_ERROR;
        }
 
-       arm_arch_state(target);
+       if (arm->core_state == ARM_STATE_AARCH64)
+               armv8_aarch64_state(target);
+       else
+               arm_arch_state(target);
 
 
-       if (armv8->is_armv7r) {
-               LOG_USER("D-Cache: %s, I-Cache: %s",
-                       state[armv8->armv8_mmu.armv8_cache.d_u_cache_enabled],
-                       state[armv8->armv8_mmu.armv8_cache.i_cache_enabled]);
-       } else {
-               LOG_USER("MMU: %s, D-Cache: %s, I-Cache: %s",
-                       state[armv8->armv8_mmu.mmu_enabled],
-                       state[armv8->armv8_mmu.armv8_cache.d_u_cache_enabled],
-                       state[armv8->armv8_mmu.armv8_cache.i_cache_enabled]);
-       }
+       LOG_USER("MMU: %s, D-Cache: %s, I-Cache: %s",
+               state[armv8->armv8_mmu.mmu_enabled],
+               state[armv8->armv8_mmu.armv8_cache.d_u_cache_enabled],
+               state[armv8->armv8_mmu.armv8_cache.i_cache_enabled]);
 
        if (arm->core_mode == ARM_MODE_ABT)
                armv8_show_fault_registers(target);
 
        if (arm->core_mode == ARM_MODE_ABT)
                armv8_show_fault_registers(target);
+
        if (target->debug_reason == DBG_REASON_WATCHPOINT)
                LOG_USER("Watchpoint triggered at PC %#08x",
                        (unsigned) armv8->dpm.wp_pc);
        if (target->debug_reason == DBG_REASON_WATCHPOINT)
                LOG_USER("Watchpoint triggered at PC %#08x",
                        (unsigned) armv8->dpm.wp_pc);
@@ -593,42 +887,42 @@ static const struct {
        const char *group;
        const char *feature;
 } armv8_regs[] = {
        const char *group;
        const char *feature;
 } armv8_regs[] = {
-       { ARMV8_R0,  "x0",  64, REG_TYPE_INT, "general", "org.gnu.gdb.aarch64.core" },
-       { ARMV8_R1,  "x1",  64, REG_TYPE_INT, "general", "org.gnu.gdb.aarch64.core" },
-       { ARMV8_R2,  "x2",  64, REG_TYPE_INT, "general", "org.gnu.gdb.aarch64.core" },
-       { ARMV8_R3,  "x3",  64, REG_TYPE_INT, "general", "org.gnu.gdb.aarch64.core" },
-       { ARMV8_R4,  "x4",  64, REG_TYPE_INT, "general", "org.gnu.gdb.aarch64.core" },
-       { ARMV8_R5,  "x5",  64, REG_TYPE_INT, "general", "org.gnu.gdb.aarch64.core" },
-       { ARMV8_R6,  "x6",  64, REG_TYPE_INT, "general", "org.gnu.gdb.aarch64.core" },
-       { ARMV8_R7,  "x7",  64, REG_TYPE_INT, "general", "org.gnu.gdb.aarch64.core" },
-       { ARMV8_R8,  "x8",  64, REG_TYPE_INT, "general", "org.gnu.gdb.aarch64.core" },
-       { ARMV8_R9,  "x9",  64, REG_TYPE_INT, "general", "org.gnu.gdb.aarch64.core" },
-       { ARMV8_R10, "x10", 64, REG_TYPE_INT, "general", "org.gnu.gdb.aarch64.core" },
-       { ARMV8_R11, "x11", 64, REG_TYPE_INT, "general", "org.gnu.gdb.aarch64.core" },
-       { ARMV8_R12, "x12", 64, REG_TYPE_INT, "general", "org.gnu.gdb.aarch64.core" },
-       { ARMV8_R13, "x13", 64, REG_TYPE_INT, "general", "org.gnu.gdb.aarch64.core" },
-       { ARMV8_R14, "x14", 64, REG_TYPE_INT, "general", "org.gnu.gdb.aarch64.core" },
-       { ARMV8_R15, "x15", 64, REG_TYPE_INT, "general", "org.gnu.gdb.aarch64.core" },
-       { ARMV8_R16, "x16", 64, REG_TYPE_INT, "general", "org.gnu.gdb.aarch64.core" },
-       { ARMV8_R17, "x17", 64, REG_TYPE_INT, "general", "org.gnu.gdb.aarch64.core" },
-       { ARMV8_R18, "x18", 64, REG_TYPE_INT, "general", "org.gnu.gdb.aarch64.core" },
-       { ARMV8_R19, "x19", 64, REG_TYPE_INT, "general", "org.gnu.gdb.aarch64.core" },
-       { ARMV8_R20, "x20", 64, REG_TYPE_INT, "general", "org.gnu.gdb.aarch64.core" },
-       { ARMV8_R21, "x21", 64, REG_TYPE_INT, "general", "org.gnu.gdb.aarch64.core" },
-       { ARMV8_R22, "x22", 64, REG_TYPE_INT, "general", "org.gnu.gdb.aarch64.core" },
-       { ARMV8_R23, "x23", 64, REG_TYPE_INT, "general", "org.gnu.gdb.aarch64.core" },
-       { ARMV8_R24, "x24", 64, REG_TYPE_INT, "general", "org.gnu.gdb.aarch64.core" },
-       { ARMV8_R25, "x25", 64, REG_TYPE_INT, "general", "org.gnu.gdb.aarch64.core" },
-       { ARMV8_R26, "x26", 64, REG_TYPE_INT, "general", "org.gnu.gdb.aarch64.core" },
-       { ARMV8_R27, "x27", 64, REG_TYPE_INT, "general", "org.gnu.gdb.aarch64.core" },
-       { ARMV8_R28, "x28", 64, REG_TYPE_INT, "general", "org.gnu.gdb.aarch64.core" },
-       { ARMV8_R29, "x29", 64, REG_TYPE_INT, "general", "org.gnu.gdb.aarch64.core" },
-       { ARMV8_R30, "x30", 64, REG_TYPE_INT, "general", "org.gnu.gdb.aarch64.core" },
+       { ARMV8_R0,  "x0",  64, REG_TYPE_UINT64, "general", "org.gnu.gdb.aarch64.core" },
+       { ARMV8_R1,  "x1",  64, REG_TYPE_UINT64, "general", "org.gnu.gdb.aarch64.core" },
+       { ARMV8_R2,  "x2",  64, REG_TYPE_UINT64, "general", "org.gnu.gdb.aarch64.core" },
+       { ARMV8_R3,  "x3",  64, REG_TYPE_UINT64, "general", "org.gnu.gdb.aarch64.core" },
+       { ARMV8_R4,  "x4",  64, REG_TYPE_UINT64, "general", "org.gnu.gdb.aarch64.core" },
+       { ARMV8_R5,  "x5",  64, REG_TYPE_UINT64, "general", "org.gnu.gdb.aarch64.core" },
+       { ARMV8_R6,  "x6",  64, REG_TYPE_UINT64, "general", "org.gnu.gdb.aarch64.core" },
+       { ARMV8_R7,  "x7",  64, REG_TYPE_UINT64, "general", "org.gnu.gdb.aarch64.core" },
+       { ARMV8_R8,  "x8",  64, REG_TYPE_UINT64, "general", "org.gnu.gdb.aarch64.core" },
+       { ARMV8_R9,  "x9",  64, REG_TYPE_UINT64, "general", "org.gnu.gdb.aarch64.core" },
+       { ARMV8_R10, "x10", 64, REG_TYPE_UINT64, "general", "org.gnu.gdb.aarch64.core" },
+       { ARMV8_R11, "x11", 64, REG_TYPE_UINT64, "general", "org.gnu.gdb.aarch64.core" },
+       { ARMV8_R12, "x12", 64, REG_TYPE_UINT64, "general", "org.gnu.gdb.aarch64.core" },
+       { ARMV8_R13, "x13", 64, REG_TYPE_UINT64, "general", "org.gnu.gdb.aarch64.core" },
+       { ARMV8_R14, "x14", 64, REG_TYPE_UINT64, "general", "org.gnu.gdb.aarch64.core" },
+       { ARMV8_R15, "x15", 64, REG_TYPE_UINT64, "general", "org.gnu.gdb.aarch64.core" },
+       { ARMV8_R16, "x16", 64, REG_TYPE_UINT64, "general", "org.gnu.gdb.aarch64.core" },
+       { ARMV8_R17, "x17", 64, REG_TYPE_UINT64, "general", "org.gnu.gdb.aarch64.core" },
+       { ARMV8_R18, "x18", 64, REG_TYPE_UINT64, "general", "org.gnu.gdb.aarch64.core" },
+       { ARMV8_R19, "x19", 64, REG_TYPE_UINT64, "general", "org.gnu.gdb.aarch64.core" },
+       { ARMV8_R20, "x20", 64, REG_TYPE_UINT64, "general", "org.gnu.gdb.aarch64.core" },
+       { ARMV8_R21, "x21", 64, REG_TYPE_UINT64, "general", "org.gnu.gdb.aarch64.core" },
+       { ARMV8_R22, "x22", 64, REG_TYPE_UINT64, "general", "org.gnu.gdb.aarch64.core" },
+       { ARMV8_R23, "x23", 64, REG_TYPE_UINT64, "general", "org.gnu.gdb.aarch64.core" },
+       { ARMV8_R24, "x24", 64, REG_TYPE_UINT64, "general", "org.gnu.gdb.aarch64.core" },
+       { ARMV8_R25, "x25", 64, REG_TYPE_UINT64, "general", "org.gnu.gdb.aarch64.core" },
+       { ARMV8_R26, "x26", 64, REG_TYPE_UINT64, "general", "org.gnu.gdb.aarch64.core" },
+       { ARMV8_R27, "x27", 64, REG_TYPE_UINT64, "general", "org.gnu.gdb.aarch64.core" },
+       { ARMV8_R28, "x28", 64, REG_TYPE_UINT64, "general", "org.gnu.gdb.aarch64.core" },
+       { ARMV8_R29, "x29", 64, REG_TYPE_UINT64, "general", "org.gnu.gdb.aarch64.core" },
+       { ARMV8_R30, "x30", 64, REG_TYPE_UINT64, "general", "org.gnu.gdb.aarch64.core" },
 
        { ARMV8_R31, "sp", 64, REG_TYPE_DATA_PTR, "general", "org.gnu.gdb.aarch64.core" },
        { ARMV8_PC,  "pc", 64, REG_TYPE_CODE_PTR, "general", "org.gnu.gdb.aarch64.core" },
 
 
        { ARMV8_R31, "sp", 64, REG_TYPE_DATA_PTR, "general", "org.gnu.gdb.aarch64.core" },
        { ARMV8_PC,  "pc", 64, REG_TYPE_CODE_PTR, "general", "org.gnu.gdb.aarch64.core" },
 
-       { ARMV8_xPSR, "CPSR", 64, REG_TYPE_INT, "general", "org.gnu.gdb.aarch64.core" },
+       { ARMV8_xPSR, "CPSR", 32, REG_TYPE_UINT32, "general", "org.gnu.gdb.aarch64.core" },
 };
 
 #define ARMV8_NUM_REGS ARRAY_SIZE(armv8_regs)
 };
 
 #define ARMV8_NUM_REGS ARRAY_SIZE(armv8_regs)
@@ -653,14 +947,20 @@ static int armv8_set_core_reg(struct reg *reg, uint8_t *buf)
 {
        struct arm_reg *armv8_reg = reg->arch_info;
        struct target *target = armv8_reg->target;
 {
        struct arm_reg *armv8_reg = reg->arch_info;
        struct target *target = armv8_reg->target;
+       struct arm *arm = target_to_arm(target);
        uint64_t value = buf_get_u64(buf, 0, 64);
 
        if (target->state != TARGET_HALTED)
                return ERROR_TARGET_NOT_HALTED;
 
        uint64_t value = buf_get_u64(buf, 0, 64);
 
        if (target->state != TARGET_HALTED)
                return ERROR_TARGET_NOT_HALTED;
 
-       buf_set_u64(reg->value, 0, 64, value);
+       if (reg == arm->cpsr) {
+               armv8_set_cpsr(arm, (uint32_t)value);
+       } else {
+               buf_set_u64(reg->value, 0, 64, value);
+               reg->valid = 1;
+       }
+
        reg->dirty = 1;
        reg->dirty = 1;
-       reg->valid = 1;
 
        return ERROR_OK;
 }
 
        return ERROR_OK;
 }
@@ -697,7 +997,7 @@ struct reg_cache *armv8_build_reg_cache(struct target *target)
 
                reg_list[i].name = armv8_regs[i].name;
                reg_list[i].size = armv8_regs[i].bits;
 
                reg_list[i].name = armv8_regs[i].name;
                reg_list[i].size = armv8_regs[i].bits;
-               reg_list[i].value = calloc(1, 4);
+               reg_list[i].value = calloc(1, 8);
                reg_list[i].dirty = 0;
                reg_list[i].valid = 0;
                reg_list[i].type = &armv8_reg_type;
                reg_list[i].dirty = 0;
                reg_list[i].valid = 0;
                reg_list[i].type = &armv8_reg_type;
@@ -733,7 +1033,7 @@ struct reg *armv8_reg_current(struct arm *arm, unsigned regnum)
 {
        struct reg *r;
 
 {
        struct reg *r;
 
-       if (regnum > 33)
+       if (regnum > (ARMV8_LAST_REG - 1))
                return NULL;
 
        r = arm->core_cache->reg_list + regnum;
                return NULL;
 
        r = arm->core_cache->reg_list + regnum;
@@ -758,14 +1058,13 @@ int armv8_get_gdb_reg_list(struct target *target,
        switch (reg_class) {
        case REG_CLASS_GENERAL:
        case REG_CLASS_ALL:
        switch (reg_class) {
        case REG_CLASS_GENERAL:
        case REG_CLASS_ALL:
-               *reg_list_size = 34;
+               *reg_list_size = ARMV8_LAST_REG;
                *reg_list = malloc(sizeof(struct reg *) * (*reg_list_size));
 
                *reg_list = malloc(sizeof(struct reg *) * (*reg_list_size));
 
-               for (i = 0; i < *reg_list_size; i++)
+               for (i = 0; i < ARMV8_LAST_REG; i++)
                                (*reg_list)[i] = armv8_reg_current(arm, i);
 
                return ERROR_OK;
                                (*reg_list)[i] = armv8_reg_current(arm, i);
 
                return ERROR_OK;
-               break;
 
        default:
                LOG_ERROR("not a valid register class type in query.");
 
        default:
                LOG_ERROR("not a valid register class type in query.");
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