armv8: factor out generic bit set/clr for debug registers

[openocd.git] / src / target / armv8.c

diff --git a/src/target/armv8.c b/src/target/armv8.c
index a2a099d66434f2467dc8e6b7988a60db1b79dcbe..2f1d5c10a5077af0cd8d1ffcef8405cd29811e00 100644 (file)
--- a/src/target/armv8.c
+++ b/src/target/armv8.c
@@ -46,11 +46,6 @@ static const char * const armv8_state_strings[] = {
 static const struct {
        const char *name;
        unsigned psr;
-       /* For user and system modes, these list indices for all registers.
-        * otherwise they're just indices for the shadow registers and SPSR.
-        */
-       unsigned short n_indices;
-       const uint8_t *indices;
 } armv8_mode_data[] = {
        /* These special modes are currently only supported
         * by ARMv6M and ARMv7M profiles */
@@ -1091,9 +1086,6 @@ static int armv8_get_core_reg32(struct reg *reg)
        struct reg *reg64;
        int retval;
 
-       LOG_DEBUG("reg.name:%s number:%i arm.num:%i value:0x%08" PRIx64,
-                       reg->name, reg->number, armv8_reg->num, buf_get_u64(reg->value, 0, 32));
-
        /* get the corresponding Aarch64 register */
        reg64 = cache->reg_list + armv8_reg->num;
        if (reg64->valid) {
@@ -1101,7 +1093,7 @@ static int armv8_get_core_reg32(struct reg *reg)
                return ERROR_OK;
        }
 
-       retval = arm->read_core_reg(target, reg, armv8_reg->num, arm->core_mode);
+       retval = arm->read_core_reg(target, reg64, armv8_reg->num, arm->core_mode);
        if (retval == ERROR_OK)
                reg->valid = reg64->valid;
 
@@ -1117,9 +1109,6 @@ static int armv8_set_core_reg32(struct reg *reg, uint8_t *buf)
        struct reg *reg64 = cache->reg_list + armv8_reg->num;
        uint32_t value = buf_get_u32(buf, 0, 32);
 
-       if (target->state != TARGET_HALTED)
-               return ERROR_TARGET_NOT_HALTED;
-
        if (reg64 == arm->cpsr) {
                armv8_set_cpsr(arm, value);
        } else {
@@ -1168,7 +1157,7 @@ struct reg_cache *armv8_build_reg_cache(struct target *target)
 
                reg_list[i].name = armv8_regs[i].name;
                reg_list[i].size = armv8_regs[i].bits;
-               reg_list[i].value = calloc(1, 8);
+               reg_list[i].value = &arch_info[i].value[0];
                reg_list[i].type = &armv8_reg_type;
                reg_list[i].arch_info = &arch_info[i];
 
@@ -1258,7 +1247,7 @@ int armv8_get_gdb_reg_list(struct target *target,
 
        if (arm->core_state == ARM_STATE_AARCH64) {
 
-               LOG_DEBUG("Creating Aarch64 register list");
+               LOG_DEBUG("Creating Aarch64 register list for target %s", target_name(target));
 
                switch (reg_class) {
                case REG_CLASS_GENERAL:
@@ -1285,7 +1274,7 @@ int armv8_get_gdb_reg_list(struct target *target,
        } else {
                struct reg_cache *cache32 = arm->core_cache->next;
 
-               LOG_DEBUG("Creating Aarch32 register list");
+               LOG_DEBUG("Creating Aarch32 register list for target %s", target_name(target));
 
                switch (reg_class) {
                case REG_CLASS_GENERAL:
@@ -1303,3 +1292,24 @@ int armv8_get_gdb_reg_list(struct target *target,
                }
        }
 }
+
+int armv8_set_dbgreg_bits(struct armv8_common *armv8, unsigned int reg, unsigned long mask, unsigned long value)
+{
+       uint32_t tmp;
+
+       /* Read register */
+       int retval = mem_ap_read_atomic_u32(armv8->debug_ap,
+                       armv8->debug_base + reg, &tmp);
+       if (ERROR_OK != retval)
+               return retval;
+
+       /* clear bitfield */
+       tmp &= ~mask;
+       /* put new value */
+       tmp |= value & mask;
+
+       /* write new value */
+       retval = mem_ap_write_atomic_u32(armv8->debug_ap,
+                       armv8->debug_base + reg, tmp);
+       return retval;
+}