- the jtag chain is examined and validated after GDB & telnet servers

[openocd.git] / src / target / armv7m.c

diff --git a/src/target/armv7m.c b/src/target/armv7m.c
index bed394854702a430af70d5a60c667b9728676a30..f1f0ac967a0d91f90f3c8cd0dbddd4e2a2f7428a 100644 (file)
--- a/src/target/armv7m.c
+++ b/src/target/armv7m.c
@@ -1,6 +1,7 @@
 /***************************************************************************
  *   Copyright (C) 2005 by Dominic Rath                                    *
  *   Dominic.Rath@gmx.de                                                   *
+ *                                                                         *
  *   Copyright (C) 2006 by Magnus Lundin                                   *
  *   lundin@mlu.mine.nu                                                    *
  *                                                                         *
@@ -62,7 +63,7 @@ char* armv7m_core_reg_list[] =
        "sp", "lr", "pc",
        "xPSR", "msp", "psp",
        /* Registers accessed through MSR instructions */
-//     "apsr", "iapsr", "ipsr", "epsr",
+       /* "apsr", "iapsr", "ipsr", "epsr", */
        "primask", "basepri", "faultmask", "control"
 };
 
@@ -73,7 +74,7 @@ char* armv7m_core_dbgreg_list[] =
        "sp", "lr", "pc",
        "xPSR", "msp", "psp",
        /* Registers accessed through MSR instructions */
-//     "dbg_apsr", "iapsr", "ipsr", "epsr",
+       /* "dbg_apsr", "iapsr", "ipsr", "epsr", */
        "primask", "basepri", "faultmask", "dbg_control"
 };
 
@@ -109,10 +110,12 @@ armv7m_core_reg_t armv7m_core_reg_list_arch_info[] =
        {18, ARMV7M_REGISTER_CORE_GP, ARMV7M_MODE_ANY, NULL, NULL}, /* PSP */
 
        /*  CORE_SP are accesible using MSR and MRS instructions */
+#if 0
 //     {0x00, ARMV7M_REGISTER_CORE_SP, ARMV7M_MODE_ANY, NULL, NULL}, /* APSR */
 //     {0x01, ARMV7M_REGISTER_CORE_SP, ARMV7M_MODE_ANY, NULL, NULL}, /* IAPSR */
 //     {0x05, ARMV7M_REGISTER_CORE_SP, ARMV7M_MODE_ANY, NULL, NULL}, /* IPSR */
 //     {0x06, ARMV7M_REGISTER_CORE_SP, ARMV7M_MODE_ANY, NULL, NULL}, /* EPSR */
+#endif
 
        {0x10, ARMV7M_REGISTER_CORE_SP, ARMV7M_MODE_ANY, NULL, NULL}, /* PRIMASK */
        {0x11, ARMV7M_REGISTER_CORE_SP, ARMV7M_MODE_ANY, NULL, NULL}, /* BASEPRI */
@@ -318,11 +321,6 @@ int armv7m_get_gdb_reg_list(target_t *target, reg_t **reg_list[], int *reg_list_
        armv7m_common_t *armv7m = target->arch_info;
        int i;
        
-       if (target->state != TARGET_HALTED)
-       {
-               return ERROR_TARGET_NOT_HALTED;
-       }
-       
        *reg_list_size = 26;
        *reg_list = malloc(sizeof(reg_t*) * (*reg_list_size));
        
@@ -331,7 +329,7 @@ int armv7m_get_gdb_reg_list(target_t *target, reg_t **reg_list[], int *reg_list_
        {
                if (i < ARMV7NUMCOREREGS)
                        (*reg_list)[i] = &armv7m->process_context->reg_list[i];
-                       //(*reg_list)[i] = &armv7m->core_cache->reg_list[i];
+                       /* (*reg_list)[i] = &armv7m->core_cache->reg_list[i]; */
                else
                        (*reg_list)[i] = &armv7m_gdb_dummy_fp_reg;
        }
@@ -343,7 +341,7 @@ int armv7m_get_gdb_reg_list(target_t *target, reg_t **reg_list[], int *reg_list_
 
 int armv7m_run_algorithm(struct target_s *target, int num_mem_params, mem_param_t *mem_params, int num_reg_params, reg_param_t *reg_params, u32 entry_point, u32 exit_point, int timeout_ms, void *arch_info)
 {
-       // get pointers to arch-specific information
+       /* get pointers to arch-specific information */
        armv7m_common_t *armv7m = target->arch_info;
        armv7m_algorithm_t *armv7m_algorithm_info = arch_info;
        enum armv7m_state core_state = armv7m->core_state;