LOG_USER("target halted due to %s, current mode: %s %s\n"
"xPSR: %#8.8" PRIx32 " pc: %#8.8" PRIx32 " %csp: %#8.8" PRIx32,
- Jim_Nvp_value2name_simple(nvp_target_debug_reason,
- target->debug_reason)->name,
+ debug_reason_name(target),
armv7m_mode_strings[armv7m->core_mode],
armv7m_exception_string(armv7m->exception_number),
buf_get_u32(armv7m->core_cache->reg_list[ARMV7M_xPSR].value, 0, 32),
}
/* convert flash writing code into a buffer in target endianness */
- for (i = 0; i < (sizeof(cortex_m3_crc_code)/sizeof(uint16_t)); i++)
+ for (i = 0; i < ARRAY_SIZE(cortex_m3_crc_code); i++)
if ((retval = target_write_u16(target, crc_algorithm->address + i*sizeof(uint16_t), cortex_m3_crc_code[i])) != ERROR_OK)
{
return retval;
}
/* convert flash writing code into a buffer in target endianness */
- for (i = 0; i < (sizeof(erase_check_code)/sizeof(uint16_t)); i++)
+ for (i = 0; i < ARRAY_SIZE(erase_check_code); i++)
target_write_u16(target, erase_check_algorithm->address + i*sizeof(uint16_t), erase_check_code[i]);
armv7m_info.common_magic = ARMV7M_COMMON_MAGIC;
if (apselsave != apsel)
dap_ap_select(swjdp, apsel);
- dap_ap_read_reg_u32(swjdp, 0xF8, &baseaddr);
+ /* NOTE: assumes we're talking to a MEM-AP, which
+ * has a base address. There are other kinds of AP,
+ * though they're not common for now. This should
+ * use the ID register to verify it's a MEM-AP.
+ */
+ dap_ap_read_reg_u32(swjdp, AP_REG_BASE, &baseaddr);
retval = swjdp_transaction_endcheck(swjdp);
command_print(CMD_CTX, "0x%8.8" PRIx32 "", baseaddr);
},
COMMAND_REGISTRATION_DONE
};
-static const struct command_registration armv7m_command_handlers[] = {
+const struct command_registration armv7m_command_handlers[] = {
{
.name = "dap",
- .mode = COMMAND_ANY,
+ .mode = COMMAND_EXEC,
.help = "Cortex DAP command group",
.chain = armv7m_exec_command_handlers,
},
COMMAND_REGISTRATION_DONE
};
-
-int armv7m_register_commands(struct command_context *cmd_ctx)
-{
- return register_commands(cmd_ctx, NULL, armv7m_command_handlers);
-}