if (armv7m->pre_restore_context)
armv7m->pre_restore_context(target);
- for (i = ARMV7M_NUM_REGS - 1; i >= 0; i--) {
+ for (i = cache->num_regs - 1; i >= 0; i--) {
if (cache->reg_list[i].dirty) {
armv7m->arm.write_core_reg(target, &cache->reg_list[i], i,
ARM_MODE_ANY, cache->reg_list[i].value);
int i;
if (reg_class == REG_CLASS_ALL)
- *reg_list_size = ARMV7M_NUM_REGS;
+ *reg_list_size = armv7m->arm.core_cache->num_regs;
else
*reg_list_size = ARMV7M_NUM_CORE_REGS;
/* refresh core register cache
* Not needed if core register cache is always consistent with target process state */
- for (unsigned i = 0; i < ARMV7M_NUM_REGS; i++) {
+ for (unsigned i = 0; i < armv7m->arm.core_cache->num_regs; i++) {
armv7m_algorithm_info->context[i] = buf_get_u32(
armv7m->arm.core_cache->reg_list[i].value,
}
}
- for (int i = ARMV7M_NUM_REGS - 1; i >= 0; i--) {
+ for (int i = armv7m->arm.core_cache->num_regs - 1; i >= 0; i--) {
uint32_t regvalue;
regvalue = buf_get_u32(armv7m->arm.core_cache->reg_list[i].value, 0, 32);
if (regvalue != armv7m_algorithm_info->context[i]) {
return cache;
}
+void armv7m_free_reg_cache(struct target *target)
+{
+ struct armv7m_common *armv7m = target_to_armv7m(target);
+ struct arm *arm = &armv7m->arm;
+ struct reg_cache *cache;
+ struct reg *reg;
+ unsigned int i;
+
+ cache = arm->core_cache;
+
+ if (!cache)
+ return;
+
+ for (i = 0; i < cache->num_regs; i++) {
+ reg = &cache->reg_list[i];
+
+ free(reg->feature);
+ free(reg->reg_data_type);
+ free(reg->value);
+ }
+
+ free(cache->reg_list[0].arch_info);
+ free(cache->reg_list);
+ free(cache);
+
+ arm->core_cache = NULL;
+}
+
static int armv7m_setup_semihosting(struct target *target, int enable)
{
/* nothing todo for armv7m */
armv7m->common_magic = ARMV7M_COMMON_MAGIC;
armv7m->fp_feature = FP_NONE;
+ armv7m->trace_config.trace_bus_id = 1;
+ /* Enable stimulus port #0 by default */
+ armv7m->trace_config.itm_ter[0] = 1;
arm->core_type = ARM_MODE_THREAD;
arm->arch_info = armv7m;
struct reg_param reg_params[2];
int retval;
- /* see contrib/loaders/checksum/armv7m_crc.s for src */
-
static const uint8_t cortex_m_crc_code[] = {
- /* main: */
- 0x02, 0x46, /* mov r2, r0 */
- 0x00, 0x20, /* movs r0, #0 */
- 0xC0, 0x43, /* mvns r0, r0 */
- 0x0A, 0x4E, /* ldr r6, CRC32XOR */
- 0x0B, 0x46, /* mov r3, r1 */
- 0x00, 0x24, /* movs r4, #0 */
- 0x0D, 0xE0, /* b ncomp */
- /* nbyte: */
- 0x11, 0x5D, /* ldrb r1, [r2, r4] */
- 0x09, 0x06, /* lsls r1, r1, #24 */
- 0x48, 0x40, /* eors r0, r0, r1 */
- 0x00, 0x25, /* movs r5, #0 */
- /* loop: */
- 0x00, 0x28, /* cmp r0, #0 */
- 0x02, 0xDA, /* bge notset */
- 0x40, 0x00, /* lsls r0, r0, #1 */
- 0x70, 0x40, /* eors r0, r0, r6 */
- 0x00, 0xE0, /* b cont */
- /* notset: */
- 0x40, 0x00, /* lsls r0, r0, #1 */
- /* cont: */
- 0x01, 0x35, /* adds r5, r5, #1 */
- 0x08, 0x2D, /* cmp r5, #8 */
- 0xF6, 0xD1, /* bne loop */
- 0x01, 0x34, /* adds r4, r4, #1 */
- /* ncomp: */
- 0x9C, 0x42, /* cmp r4, r3 */
- 0xEF, 0xD1, /* bne nbyte */
- 0x00, 0xBE, /* bkpt #0 */
- 0xB7, 0x1D, 0xC1, 0x04 /* CRC32XOR: .word 0x04c11db7 */
+#include "../../contrib/loaders/checksum/armv7m_crc.inc"
};
retval = target_alloc_working_area(target, sizeof(cortex_m_crc_code), &crc_algorithm);
struct armv7m_algorithm armv7m_info;
int retval;
- /* see contrib/loaders/erase_check/armv7m_erase_check.s for src */
-
static const uint8_t erase_check_code[] = {
- /* loop: */
- 0x03, 0x78, /* ldrb r3, [r0] */
- 0x01, 0x30, /* adds r0, #1 */
- 0x1A, 0x40, /* ands r2, r2, r3 */
- 0x01, 0x39, /* subs r1, r1, #1 */
- 0xFA, 0xD1, /* bne loop */
- 0x00, 0xBE /* bkpt #0 */
+#include "../../contrib/loaders/erase_check/armv7m_erase_check.inc"
};
/* make sure we have a working area */
retval = target_write_buffer(target, erase_check_algorithm->address,
sizeof(erase_check_code), (uint8_t *)erase_check_code);
if (retval != ERROR_OK)
- return retval;
+ goto cleanup;
armv7m_info.common_magic = ARMV7M_COMMON_MAGIC;
armv7m_info.core_mode = ARM_MODE_THREAD;
destroy_reg_param(®_params[1]);
destroy_reg_param(®_params[2]);
+cleanup:
target_free_working_area(target, erase_check_algorithm);
return retval;