Code Review / openocd.git / blobdiff
? search:
summary | shortlog | log | commit | commitdiff | review | tree
raw | inline | side by side
target/armv7m: minor fixes of target algo exit point check
[openocd.git] / src / target / armv7m.c
diff --git a/src/target/armv7m.c b/src/target/armv7m.c
index 1b4e5b154db16fe3af5f0ea134383d8d464b1ea3..837ccc94e75890ecd94bbcd7ef7d8e099560242f 100644 (file)
--- a/src/target/armv7m.c
+++ b/src/target/armv7m.c
@@ -191,7 +191,7 @@ static int armv7m_get_core_reg(struct reg *reg)
        if (target->state != TARGET_HALTED)
                return ERROR_TARGET_NOT_HALTED;
 
-       retval = arm->read_core_reg(target, reg, armv7m_reg->num, arm->core_mode);
+       retval = arm->read_core_reg(target, reg, reg->number, arm->core_mode);
 
        return retval;
 }
@@ -205,8 +205,8 @@ static int armv7m_set_core_reg(struct reg *reg, uint8_t *buf)
                return ERROR_TARGET_NOT_HALTED;
 
        buf_cpy(buf, reg->value, reg->size);
-       reg->dirty = 1;
-       reg->valid = 1;
+       reg->dirty = true;
+       reg->valid = true;
 
        return ERROR_OK;
 }
@@ -244,8 +244,8 @@ static int armv7m_read_core_reg(struct target *target, struct reg *r,
                buf_set_u32(armv7m->arm.core_cache->reg_list[num].value, 0, 32, reg_value);
        }
 
-       armv7m->arm.core_cache->reg_list[num].valid = 1;
-       armv7m->arm.core_cache->reg_list[num].dirty = 0;
+       armv7m->arm.core_cache->reg_list[num].valid = true;
+       armv7m->arm.core_cache->reg_list[num].dirty = false;
 
        return retval;
 }
@@ -283,8 +283,8 @@ static int armv7m_write_core_reg(struct target *target, struct reg *r,
                        goto out_error;
        }
 
-       armv7m->arm.core_cache->reg_list[num].valid = 1;
-       armv7m->arm.core_cache->reg_list[num].dirty = 0;
+       armv7m->arm.core_cache->reg_list[num].valid = true;
+       armv7m->arm.core_cache->reg_list[num].dirty = false;
 
        return ERROR_OK;
 
@@ -379,7 +379,8 @@ int armv7m_start_algorithm(struct target *target,
        }
 
        for (int i = 0; i < num_mem_params; i++) {
-               /* TODO: Write only out params */
+               if (mem_params[i].direction == PARAM_IN)
+                       continue;
                retval = target_write_buffer(target, mem_params[i].address,
                                mem_params[i].size,
                                mem_params[i].value);
@@ -388,6 +389,9 @@ int armv7m_start_algorithm(struct target *target,
        }
 
        for (int i = 0; i < num_reg_params; i++) {
+               if (reg_params[i].direction == PARAM_IN)
+                       continue;
+
                struct reg *reg =
                        register_get_by_name(armv7m->arm.core_cache, reg_params[i].reg_name, 0);
 /*             uint32_t regvalue; */
@@ -407,6 +411,23 @@ int armv7m_start_algorithm(struct target *target,
                armv7m_set_core_reg(reg, reg_params[i].value);
        }
 
+       {
+               /*
+                * Ensure xPSR.T is set to avoid trying to run things in arm
+                * (non-thumb) mode, which armv7m does not support.
+                *
+                * We do this by setting the entirety of xPSR, which should
+                * remove all the unknowns about xPSR state.
+                *
+                * Because xPSR.T is populated on reset from the vector table,
+                * it might be 0 if the vector table has "bad" data in it.
+                */
+               struct reg *reg = &armv7m->arm.core_cache->reg_list[ARMV7M_xPSR];
+               buf_set_u32(reg->value, 0, 32, 0x01000000);
+               reg->valid = true;
+               reg->dirty = true;
+       }
+
        if (armv7m_algorithm_info->core_mode != ARM_MODE_ANY &&
                        armv7m_algorithm_info->core_mode != core_mode) {
 
@@ -419,8 +440,8 @@ int armv7m_start_algorithm(struct target *target,
                LOG_DEBUG("setting core_mode: 0x%2.2x", armv7m_algorithm_info->core_mode);
                buf_set_u32(armv7m->arm.core_cache->reg_list[ARMV7M_CONTROL].value,
                        0, 1, armv7m_algorithm_info->core_mode);
-               armv7m->arm.core_cache->reg_list[ARMV7M_CONTROL].dirty = 1;
-               armv7m->arm.core_cache->reg_list[ARMV7M_CONTROL].valid = 1;
+               armv7m->arm.core_cache->reg_list[ARMV7M_CONTROL].dirty = true;
+               armv7m->arm.core_cache->reg_list[ARMV7M_CONTROL].valid = true;
        }
 
        /* save previous core mode */
@@ -441,7 +462,6 @@ int armv7m_wait_algorithm(struct target *target,
        struct armv7m_common *armv7m = target_to_armv7m(target);
        struct armv7m_algorithm *armv7m_algorithm_info = arch_info;
        int retval = ERROR_OK;
-       uint32_t pc;
 
        /* NOTE: armv7m_run_algorithm requires that each algorithm uses a software breakpoint
         * at the exit point */
@@ -463,12 +483,14 @@ int armv7m_wait_algorithm(struct target *target,
                return ERROR_TARGET_TIMEOUT;
        }
 
-       armv7m->load_core_reg_u32(target, 15, &pc);
-       if (exit_point && (pc != exit_point)) {
-               LOG_DEBUG("failed algorithm halted at 0x%" PRIx32 ", expected 0x%" TARGET_PRIxADDR,
-                       pc,
-                       exit_point);
-               return ERROR_TARGET_TIMEOUT;
+       if (exit_point) {
+               /* PC value has been cached in cortex_m_debug_entry() */
+               uint32_t pc = buf_get_u32(armv7m->arm.pc->value, 0, 32);
+               if (pc != exit_point) {
+                       LOG_DEBUG("failed algorithm halted at 0x%" PRIx32 ", expected 0x%" TARGET_PRIxADDR,
+                                         pc, exit_point);
+                       return ERROR_TARGET_ALGO_EXIT;
+               }
        }
 
        /* Read memory values to mem_params[] */
@@ -514,8 +536,8 @@ int armv7m_wait_algorithm(struct target *target,
                                armv7m_algorithm_info->context[i]);
                        buf_set_u32(armv7m->arm.core_cache->reg_list[i].value,
                                0, 32, armv7m_algorithm_info->context[i]);
-                       armv7m->arm.core_cache->reg_list[i].valid = 1;
-                       armv7m->arm.core_cache->reg_list[i].dirty = 1;
+                       armv7m->arm.core_cache->reg_list[i].valid = true;
+                       armv7m->arm.core_cache->reg_list[i].dirty = true;
                }
        }
 
@@ -524,8 +546,8 @@ int armv7m_wait_algorithm(struct target *target,
                LOG_DEBUG("restoring core_mode: 0x%2.2x", armv7m_algorithm_info->core_mode);
                buf_set_u32(armv7m->arm.core_cache->reg_list[ARMV7M_CONTROL].value,
                        0, 1, armv7m_algorithm_info->core_mode);
-               armv7m->arm.core_cache->reg_list[ARMV7M_CONTROL].dirty = 1;
-               armv7m->arm.core_cache->reg_list[ARMV7M_CONTROL].valid = 1;
+               armv7m->arm.core_cache->reg_list[ARMV7M_CONTROL].dirty = true;
+               armv7m->arm.core_cache->reg_list[ARMV7M_CONTROL].valid = true;
        }
 
        armv7m->arm.core_mode = armv7m_algorithm_info->core_mode;
@@ -541,7 +563,7 @@ int armv7m_arch_state(struct target *target)
        uint32_t ctrl, sp;
 
        /* avoid filling log waiting for fileio reply */
-       if (target->semihosting->hit_fileio)
+       if (target->semihosting && target->semihosting->hit_fileio)
                return ERROR_OK;
 
        ctrl = buf_get_u32(arm->core_cache->reg_list[ARMV7M_CONTROL].value, 0, 32);
@@ -556,8 +578,8 @@ int armv7m_arch_state(struct target *target)
                buf_get_u32(arm->pc->value, 0, 32),
                (ctrl & 0x02) ? 'p' : 'm',
                sp,
-               target->semihosting->is_active ? ", semihosting" : "",
-               target->semihosting->is_fileio ? " fileio" : "");
+               (target->semihosting && target->semihosting->is_active) ? ", semihosting" : "",
+               (target->semihosting && target->semihosting->is_fileio) ? " fileio" : "");
 
        return ERROR_OK;
 }
@@ -598,8 +620,8 @@ struct reg_cache *armv7m_build_reg_cache(struct target *target)
                if (storage_size < 4)
                        storage_size = 4;
                reg_list[i].value = calloc(1, storage_size);
-               reg_list[i].dirty = 0;
-               reg_list[i].valid = 0;
+               reg_list[i].dirty = false;
+               reg_list[i].valid = false;
                reg_list[i].type = &armv7m_reg_type;
                reg_list[i].arch_info = &arch_info[i];
 
@@ -674,7 +696,7 @@ int armv7m_init_arch_info(struct target *target, struct armv7m_common *armv7m)
        /* Enable stimulus port #0 by default */
        armv7m->trace_config.itm_ter[0] = 1;
 
-       arm->core_type = ARM_MODE_THREAD;
+       arm->core_type = ARM_CORE_TYPE_M_PROFILE;
        arm->arch_info = armv7m;
        arm->setup_semihosting = armv7m_setup_semihosting;
 
Open On-Chip Debugger

Linking to existing account procedure

If you already have an account and want to add another login method you MUST first sign in with your existing account and then change URL to read https://review.openocd.org/login/?link to get to this page again but this time it'll work for linking. Thank you.

SSH host keys fingerprints

1024 SHA256:YKx8b7u5ZWdcbp7/4AeXNaqElP49m6QrwfXaqQGJAOk gerrit-code-review@openocd.zylin.com (DSA)
384 SHA256:jHIbSQa4REvwCFG4cq5LBlBLxmxSqelQPem/EXIrxjk gerrit-code-review@openocd.org (ECDSA)
521 SHA256:UAOPYkU9Fjtcao0Ul/Rrlnj/OsQvt+pgdYSZ4jOYdgs gerrit-code-review@openocd.org (ECDSA)
256 SHA256:A13M5QlnozFOvTllybRZH6vm7iSt0XLxbA48yfc2yfY gerrit-code-review@openocd.org (ECDSA)
256 SHA256:spYMBqEYoAOtK7yZBrcwE8ZpYt6b68Cfh9yEVetvbXg gerrit-code-review@openocd.org (ED25519)
+--[ED25519 256]--+
|=..              |
|+o..   .         |
|*.o   . .        |
|+B . . .         |
|Bo. = o S        |
|Oo.+ + =         |
|oB=.* = . o      |
| =+=.+   + E     |
|. .=o   . o      |
+----[SHA256]-----+
2048 SHA256:0Onrb7/PHjpo6iVZ7xQX2riKN83FJ3KGU0TvI0TaFG4 gerrit-code-review@openocd.zylin.com (RSA)