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Remove FSF address from GPL notices
[openocd.git] / src / target / armv7a_cache.c
diff --git a/src/target/armv7a_cache.c b/src/target/armv7a_cache.c
index 94fa09703c8164436c8663000ab3ea6cc456fd7c..7af3e6d4e8a2d6ff1cf8ba9917613fcea9fe1f0b 100644 (file)
--- a/src/target/armv7a_cache.c
+++ b/src/target/armv7a_cache.c
@@ -11,6 +11,9 @@
  *   but WITHOUT ANY WARRANTY; without even the implied warranty of        *
  *   MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the         *
  *   GNU General Public License for more details.                          *
+ *                                                                         *
+ *   You should have received a copy of the GNU General Public License     *
+ *   along with this program.  If not, see <http://www.gnu.org/licenses/>. *
  ***************************************************************************/
 
 #ifdef HAVE_CONFIG_H
@@ -35,7 +38,7 @@ static int armv7a_l1_d_cache_sanity_check(struct target *target)
 
        /*  check that cache data is on at target halt */
        if (!armv7a->armv7a_mmu.armv7a_cache.d_u_cache_enabled) {
-               LOG_DEBUG("l1 data cache is not enabled");
+               LOG_DEBUG("data cache is not enabled");
                return ERROR_TARGET_INVALID;
        }
 
@@ -53,7 +56,7 @@ static int armv7a_l1_i_cache_sanity_check(struct target *target)
 
        /*  check that cache data is on at target halt */
        if (!armv7a->armv7a_mmu.armv7a_cache.i_cache_enabled) {
-               LOG_DEBUG("l1 data cache is not enabled");
+               LOG_DEBUG("instruction cache is not enabled");
                return ERROR_TARGET_INVALID;
        }
 
@@ -152,13 +155,14 @@ int armv7a_cache_auto_flush_all_data(struct target *target)
 }
 
 
-static int armv7a_l1_d_cache_inval_virt(struct target *target, uint32_t virt,
+int armv7a_l1_d_cache_inval_virt(struct target *target, uint32_t virt,
                                        uint32_t size)
 {
        struct armv7a_common *armv7a = target_to_armv7a(target);
        struct arm_dpm *dpm = armv7a->arm.dpm;
        struct armv7a_cache_common *armv7a_cache = &armv7a->armv7a_mmu.armv7a_cache;
-       uint32_t i, linelen = armv7a_cache->dminline;
+       uint32_t linelen = armv7a_cache->dminline;
+       uint32_t va_line, va_end;
        int retval;
 
        retval = armv7a_l1_d_cache_sanity_check(target);
@@ -169,15 +173,39 @@ static int armv7a_l1_d_cache_inval_virt(struct target *target, uint32_t virt,
        if (retval != ERROR_OK)
                goto done;
 
-       for (i = 0; i < size; i += linelen) {
-               uint32_t offs = virt + i;
+       va_line = virt & (-linelen);
+       va_end = virt + size;
 
-               /* DCIMVAC - Clean and invalidate data cache line by VA to PoC. */
+       /* handle unaligned start */
+       if (virt != va_line) {
+               /* DCCIMVAC */
                retval = dpm->instr_write_data_r0(dpm,
-                               ARMV4_5_MCR(15, 0, 0, 7, 6, 1), offs);
+                               ARMV4_5_MCR(15, 0, 0, 7, 14, 1), va_line);
                if (retval != ERROR_OK)
                        goto done;
+               va_line += linelen;
        }
+
+       /* handle unaligned end */
+       if ((va_end & (linelen-1)) != 0) {
+               va_end &= (-linelen);
+               /* DCCIMVAC */
+               retval = dpm->instr_write_data_r0(dpm,
+                               ARMV4_5_MCR(15, 0, 0, 7, 14, 1), va_end);
+               if (retval != ERROR_OK)
+                       goto done;
+       }
+
+       while (va_line < va_end) {
+               /* DCIMVAC - Invalidate data cache line by VA to PoC. */
+               retval = dpm->instr_write_data_r0(dpm,
+                               ARMV4_5_MCR(15, 0, 0, 7, 6, 1), va_line);
+               if (retval != ERROR_OK)
+                       goto done;
+               va_line += linelen;
+       }
+
+       dpm->finish(dpm);
        return retval;
 
 done:
@@ -193,7 +221,48 @@ int armv7a_l1_d_cache_clean_virt(struct target *target, uint32_t virt,
        struct armv7a_common *armv7a = target_to_armv7a(target);
        struct arm_dpm *dpm = armv7a->arm.dpm;
        struct armv7a_cache_common *armv7a_cache = &armv7a->armv7a_mmu.armv7a_cache;
-       uint32_t i, linelen = armv7a_cache->dminline;
+       uint32_t linelen = armv7a_cache->dminline;
+       uint32_t va_line, va_end;
+       int retval;
+
+       retval = armv7a_l1_d_cache_sanity_check(target);
+       if (retval != ERROR_OK)
+               return retval;
+
+       retval = dpm->prepare(dpm);
+       if (retval != ERROR_OK)
+               goto done;
+
+       va_line = virt & (-linelen);
+       va_end = virt + size;
+
+       while (va_line < va_end) {
+               /* DCCMVAC - Data Cache Clean by MVA to PoC */
+               retval = dpm->instr_write_data_r0(dpm,
+                               ARMV4_5_MCR(15, 0, 0, 7, 10, 1), va_line);
+               if (retval != ERROR_OK)
+                       goto done;
+               va_line += linelen;
+       }
+
+       dpm->finish(dpm);
+       return retval;
+
+done:
+       LOG_ERROR("d-cache invalidate failed");
+       dpm->finish(dpm);
+
+       return retval;
+}
+
+int armv7a_l1_d_cache_flush_virt(struct target *target, uint32_t virt,
+                                       unsigned int size)
+{
+       struct armv7a_common *armv7a = target_to_armv7a(target);
+       struct arm_dpm *dpm = armv7a->arm.dpm;
+       struct armv7a_cache_common *armv7a_cache = &armv7a->armv7a_mmu.armv7a_cache;
+       uint32_t linelen = armv7a_cache->dminline;
+       uint32_t va_line, va_end;
        int retval;
 
        retval = armv7a_l1_d_cache_sanity_check(target);
@@ -204,16 +273,19 @@ int armv7a_l1_d_cache_clean_virt(struct target *target, uint32_t virt,
        if (retval != ERROR_OK)
                goto done;
 
-       for (i = 0; i < size; i += linelen) {
-               uint32_t offs = virt + i;
+       va_line = virt & (-linelen);
+       va_end = virt + size;
 
-               /* FIXME: do we need DCCVAC or DCCVAU */
-               /* FIXME: in both cases it is not enough for i-cache */
+       while (va_line < va_end) {
+               /* DCCIMVAC */
                retval = dpm->instr_write_data_r0(dpm,
-                               ARMV4_5_MCR(15, 0, 0, 7, 10, 1), offs);
+                               ARMV4_5_MCR(15, 0, 0, 7, 14, 1), va_line);
                if (retval != ERROR_OK)
                        goto done;
+               va_line += linelen;
        }
+
+       dpm->finish(dpm);
        return retval;
 
 done:
@@ -304,6 +376,14 @@ done:
        return retval;
 }
 
+int armv7a_cache_flush_virt(struct target *target, uint32_t virt,
+                               uint32_t size)
+{
+       armv7a_l1_d_cache_flush_virt(target, virt, size);
+       armv7a_l2x_cache_flush_virt(target, virt, size);
+
+       return ERROR_OK;
+}
 
 /*
  * We assume that target core was chosen correctly. It means if same data
@@ -319,41 +399,11 @@ int armv7a_cache_auto_flush_on_write(struct target *target, uint32_t virt,
                                        uint32_t size)
 {
        struct armv7a_common *armv7a = target_to_armv7a(target);
-       int retval = ERROR_OK;
 
        if (!armv7a->armv7a_mmu.armv7a_cache.auto_cache_enabled)
                return ERROR_OK;
 
-       armv7a_l1_d_cache_clean_virt(target, virt, size);
-       armv7a_l2x_cache_flush_virt(target, virt, size);
-
-       if (target->smp) {
-               struct target_list *head;
-               struct target *curr;
-               head = target->head;
-               while (head != (struct target_list *)NULL) {
-                       curr = head->target;
-                       if (curr->state == TARGET_HALTED) {
-                               retval = armv7a_l1_i_cache_inval_all(curr);
-                               if (retval != ERROR_OK)
-                                       return retval;
-                               retval = armv7a_l1_d_cache_inval_virt(target,
-                                               virt, size);
-                               if (retval != ERROR_OK)
-                                       return retval;
-                       }
-                       head = head->next;
-               }
-       } else {
-               retval = armv7a_l1_i_cache_inval_all(target);
-               if (retval != ERROR_OK)
-                       return retval;
-               retval = armv7a_l1_d_cache_inval_virt(target, virt, size);
-               if (retval != ERROR_OK)
-                       return retval;
-       }
-
-       return retval;
+       return armv7a_cache_flush_virt(target, virt, size);
 }
 
 COMMAND_HANDLER(arm7a_l1_cache_info_cmd)
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