#include "armv4_5.h"
#include "armv4_5_mmu.h"
#include "armv4_5_cache.h"
-
-
-typedef enum armv7a_state
-{
- ARMV7A_STATE_ARM,
- ARMV7A_STATE_THUMB,
- ARMV7A_STATE_JAZELLE,
- ARMV7A_STATE_THUMBEE,
-} armv7a_state_t;
+#include "arm_dpm.h"
enum
{
ARM_CPSR = 16
}
;
-/* offsets into armv4_5 core register cache */
-enum
-{
- ARMV7A_CPSR = 31,
- ARMV7A_SPSR_FIQ = 32,
- ARMV7A_SPSR_IRQ = 33,
- ARMV7A_SPSR_SVC = 34,
- ARMV7A_SPSR_ABT = 35,
- ARMV7A_SPSR_UND = 36
-};
#define ARMV7_COMMON_MAGIC 0x0A450999
struct armv7a_common
{
+ struct arm armv4_5_common;
int common_magic;
struct reg_cache *core_cache;
- enum armv7a_state core_state;
/* arm adp debug port */
struct swjdp_common swjdp_info;
/* Core Debug Unit */
+ struct arm_dpm dpm;
uint32_t debug_base;
uint8_t debug_ap;
uint8_t memory_ap;
/* Cache and Memory Management Unit */
struct armv4_5_mmu_common armv4_5_mmu;
- struct arm armv4_5_common;
int (*read_cp15)(struct target *target,
uint32_t op1, uint32_t op2,
int common_magic;
enum armv4_5_mode core_mode;
- enum armv7a_state core_state;
+ enum armv4_5_state core_state;
};
struct armv7a_core_reg
int armv7a_arch_state(struct target *target);
struct reg_cache *armv7a_build_reg_cache(struct target *target,
struct armv7a_common *armv7a_common);
-int armv7a_register_commands(struct command_context *cmd_ctx);
int armv7a_init_arch_info(struct target *target, struct armv7a_common *armv7a);
+extern const struct command_registration armv7a_command_handlers[];
+
#endif /* ARMV4_5_H */