ARMV7A_MODE_ANY = -1
} armv7a_t;
-char **armv7a_mode_strings;
+extern char **armv7a_mode_strings;
typedef enum armv7a_state
{
extern char *armv7a_state_strings[];
-int armv7a_core_reg_map[8][17];
+extern int armv7a_core_reg_map[8][17];
#define ARMV7A_CORE_REG_MODE(cache, mode, num) \
cache->reg_list[armv7a_core_reg_map[armv7a_mode_to_number(mode)][num]]
#define ARMV4_5_COMMON_MAGIC 0x0A450A45
#define ARMV7_COMMON_MAGIC 0x0A450999
+/* VA to PA translation operations opc2 values*/
+#define V2PCWPR 0
+#define V2PCWPW 1
+#define V2PCWUR 2
+#define V2PCWUW 3
+#define V2POWPR 4
+#define V2POWPW 5
+#define V2POWUR 6
+#define V2POWUW 7
+
typedef struct armv7a_common_s
{
int common_magic;
/* arm adp debug port */
swjdp_common_t swjdp_info;
+
+ /* Core Debug Unit */
+ uint32_t debug_base;
+ uint8_t debug_ap;
+ uint8_t memory_ap;
+
+ /* Cache and Memory Management Unit */
armv4_5_mmu_common_t armv4_5_mmu;
armv4_5_common_t armv4_5_common;
- void *arch_info;
// int (*full_context)(struct target_s *target);
// int (*read_core_reg)(struct target_s *target, int num, enum armv7a_mode mode);
uint32_t CRn, uint32_t CRm, uint32_t value);
int (*examine_debug_reason)(target_t *target);
- void (*pre_debug_entry)(target_t *target);
void (*post_debug_entry)(target_t *target);
void (*pre_restore_context)(target_t *target);
} armv7a_common_t;
+static inline struct armv7a_common_s *
+target_to_armv7a(struct target_s *target)
+{
+ return container_of(target->arch_info, struct armv7a_common_s,
+ armv4_5_common);
+}
+
typedef struct armv7a_algorithm_s
{
int common_magic;
case ARMV7A_MODE_MON: return 7; break;
case ARMV7A_MODE_ANY: return 0; break; /* map MODE_ANY to user mode */
default:
- LOG_ERROR("invalid mode value encountered");
+ LOG_ERROR("invalid mode value encountered, val %d", mode);
return -1;
}
}
};
-#endif /* ARMV4_5_H */
\ No newline at end of file
+#endif /* ARMV4_5_H */