+ struct arm_dpm *dpm = armv7a->arm.dpm;
+ uint32_t cache_selected, clidr, ctr;
+ uint32_t cache_i_reg, cache_d_reg;
+ struct armv7a_cache_common *cache = &(armv7a->armv7a_mmu.armv7a_cache);
+ if (!armv7a->is_armv7r)
+ armv7a_read_ttbcr(target);
+ retval = dpm->prepare(dpm);
+ if (retval != ERROR_OK)
+ goto done;
+
+ /* retrieve CTR
+ * mrc p15, 0, r0, c0, c0, 1 @ read ctr */
+ retval = dpm->instr_read_data_r0(dpm,
+ ARMV4_5_MRC(15, 0, 0, 0, 0, 1),
+ &ctr);
+ if (retval != ERROR_OK)
+ goto done;
+
+ cache->iminline = 4UL << (ctr & 0xf);
+ cache->dminline = 4UL << ((ctr & 0xf0000) >> 16);
+ LOG_DEBUG("ctr %" PRIx32 " ctr.iminline %" PRId32 " ctr.dminline %" PRId32,
+ ctr, cache->iminline, cache->dminline);
+
+ /* retrieve CLIDR
+ * mrc p15, 1, r0, c0, c0, 1 @ read clidr */
+ retval = dpm->instr_read_data_r0(dpm,
+ ARMV4_5_MRC(15, 1, 0, 0, 0, 1),
+ &clidr);
+ if (retval != ERROR_OK)
+ goto done;
+ clidr = (clidr & 0x7000000) >> 23;
+ LOG_INFO("number of cache level %" PRIx32, (uint32_t)(clidr / 2));
+ if ((clidr / 2) > 1) {
+ /* FIXME not supported present in cortex A8 and later */
+ /* in cortex A7, A15 */
+ LOG_ERROR("cache l2 present :not supported");
+ }
+ /* retrieve selected cache
+ * MRC p15, 2,<Rd>, c0, c0, 0; Read CSSELR */
+ retval = dpm->instr_read_data_r0(dpm,
+ ARMV4_5_MRC(15, 2, 0, 0, 0, 0),
+ &cache_selected);
+ if (retval != ERROR_OK)
+ goto done;
+
+ retval = armv7a->arm.mrc(target, 15,
+ 2, 0, /* op1, op2 */
+ 0, 0, /* CRn, CRm */
+ &cache_selected);
+ if (retval != ERROR_OK)
+ goto done;
+ /* select instruction cache
+ * MCR p15, 2,<Rd>, c0, c0, 0; Write CSSELR
+ * [0] : 1 instruction cache selection , 0 data cache selection */
+ retval = dpm->instr_write_data_r0(dpm,
+ ARMV4_5_MRC(15, 2, 0, 0, 0, 0),
+ 1);
+ if (retval != ERROR_OK)
+ goto done;
+
+ /* read CCSIDR
+ * MRC P15,1,<RT>,C0, C0,0 ;on cortex A9 read CCSIDR
+ * [2:0] line size 001 eight word per line
+ * [27:13] NumSet 0x7f 16KB, 0xff 32Kbytes, 0x1ff 64Kbytes */
+ retval = dpm->instr_read_data_r0(dpm,
+ ARMV4_5_MRC(15, 1, 0, 0, 0, 0),
+ &cache_i_reg);
+ if (retval != ERROR_OK)
+ goto done;
+
+ /* select data cache*/
+ retval = dpm->instr_write_data_r0(dpm,
+ ARMV4_5_MRC(15, 2, 0, 0, 0, 0),
+ 0);
+ if (retval != ERROR_OK)
+ goto done;
+
+ retval = dpm->instr_read_data_r0(dpm,
+ ARMV4_5_MRC(15, 1, 0, 0, 0, 0),
+ &cache_d_reg);
+ if (retval != ERROR_OK)
+ goto done;
+
+ /* restore selected cache */
+ dpm->instr_write_data_r0(dpm,
+ ARMV4_5_MRC(15, 2, 0, 0, 0, 0),
+ cache_selected);
+
+ if (retval != ERROR_OK)
+ goto done;
+ dpm->finish(dpm);
+
+ /* put fake type */
+ cache->d_u_size.linelen = 16 << (cache_d_reg & 0x7);
+ cache->d_u_size.cachesize = (((cache_d_reg >> 13) & 0x7fff)+1)/8;
+ cache->d_u_size.nsets = (cache_d_reg >> 13) & 0x7fff;
+ cache->d_u_size.associativity = ((cache_d_reg >> 3) & 0x3ff) + 1;
+ /* compute info for set way operation on cache */
+ cache->d_u_size.index_shift = (cache_d_reg & 0x7) + 4;
+ cache->d_u_size.index = (cache_d_reg >> 13) & 0x7fff;
+ cache->d_u_size.way = ((cache_d_reg >> 3) & 0x3ff);
+ cache->d_u_size.way_shift = cache->d_u_size.way + 1;
+ {
+ int i = 0;
+ while (((cache->d_u_size.way_shift >> i) & 1) != 1)
+ i++;
+ cache->d_u_size.way_shift = 32-i;