+ int i=0;
+ while(((cache->d_u_size.way_shift >> i) & 1)!=1) i++;
+ cache->d_u_size.way_shift = 32-i;
+ }
+ /*LOG_INFO("data cache index %d << %d, way %d << %d",
+ cache->d_u_size.index, cache->d_u_size.index_shift,
+ cache->d_u_size.way, cache->d_u_size.way_shift);
+
+ LOG_INFO("data cache %d bytes %d KBytes asso %d ways",
+ cache->d_u_size.linelen,
+ cache->d_u_size.cachesize,
+ cache->d_u_size.associativity
+ );*/
+ cache->i_size.linelen = 16 << (cache_i_reg & 0x7);
+ cache->i_size.associativity = ((cache_i_reg >> 3) & 0x3ff) +1;
+ cache->i_size.nsets = (cache_i_reg >> 13) & 0x7fff;
+ cache->i_size.cachesize = (((cache_i_reg >> 13) & 0x7fff)+1)/8;
+ /* compute info for set way operation on cache */
+ cache->i_size.index_shift = (cache_i_reg & 0x7) + 4;
+ cache->i_size.index = (cache_i_reg >> 13) & 0x7fff;
+ cache->i_size.way = ((cache_i_reg >> 3) & 0x3ff);
+ cache->i_size.way_shift = cache->i_size.way+1;
+ {
+ int i=0;
+ while(((cache->i_size.way_shift >> i) & 1)!=1) i++;
+ cache->i_size.way_shift = 32-i;
+ }
+ /*LOG_INFO("instruction cache index %d << %d, way %d << %d",
+ cache->i_size.index, cache->i_size.index_shift,
+ cache->i_size.way, cache->i_size.way_shift);
+
+ LOG_INFO("instruction cache %d bytes %d KBytes asso %d ways",
+ cache->i_size.linelen,
+ cache->i_size.cachesize,
+ cache->i_size.associativity
+ );*/
+ /* if no l2 cache initialize l1 data cache flush function function */
+ if (armv7a->armv7a_mmu.armv7a_cache.flush_all_data_cache == NULL)
+ {
+ armv7a->armv7a_mmu.armv7a_cache.display_cache_info =
+ armv7a_handle_inner_cache_info_command;
+ armv7a->armv7a_mmu.armv7a_cache.flush_all_data_cache =
+ armv7a_flush_all_data;
+ }
+ armv7a->armv7a_mmu.armv7a_cache.ctype = 0;
+
+done:
+ dpm->finish(dpm);
+ armv7a_read_mpidr(target);
+ return retval;
+
+}
+
+
+
+int armv7a_init_arch_info(struct target *target, struct armv7a_common *armv7a)
+{
+ struct arm *armv4_5 = &armv7a->armv4_5_common;
+ armv4_5->arch_info = armv7a;
+ target->arch_info = &armv7a->armv4_5_common;
+ /* target is useful in all function arm v4 5 compatible */
+ armv7a->armv4_5_common.target = target;
+ armv7a->armv4_5_common.common_magic = ARM_COMMON_MAGIC;
+ armv7a->common_magic = ARMV7_COMMON_MAGIC;
+ armv7a->armv7a_mmu.armv7a_cache.l2_cache = NULL;
+ armv7a->armv7a_mmu.armv7a_cache.ctype = -1;
+ armv7a->armv7a_mmu.armv7a_cache.flush_all_data_cache = NULL;
+ armv7a->armv7a_mmu.armv7a_cache.display_cache_info = NULL;
+ return ERROR_OK;
+}
+
+int armv7a_arch_state(struct target *target)
+{
+ static const char *state[] =
+ {
+ "disabled", "enabled"
+ };
+
+ struct armv7a_common *armv7a = target_to_armv7a(target);
+ struct arm *armv4_5 = &armv7a->armv4_5_common;
+
+ if (armv7a->common_magic != ARMV7_COMMON_MAGIC)
+ {
+ LOG_ERROR("BUG: called for a non-ARMv7A target");
+ return ERROR_INVALID_ARGUMENTS;
+ }
+
+ arm_arch_state(target);
+
+ LOG_USER("MMU: %s, D-Cache: %s, I-Cache: %s",
+ state[armv7a->armv7a_mmu.mmu_enabled],
+ state[armv7a->armv7a_mmu.armv7a_cache.d_u_cache_enabled],
+ state[armv7a->armv7a_mmu.armv7a_cache.i_cache_enabled]);
+
+ if (armv4_5->core_mode == ARM_MODE_ABT)
+ armv7a_show_fault_registers(target);
+ if (target->debug_reason == DBG_REASON_WATCHPOINT)
+ LOG_USER("Watchpoint triggered at PC %#08x",
+ (unsigned) armv7a->dpm.wp_pc);
+
+ return ERROR_OK;
+}
+
+static const struct command_registration l2_cache_commands[] = {