target/cortex_m: fix clang static analyzer warning

[openocd.git] / src / target / armv4_5_cache.h

diff --git a/src/target/armv4_5_cache.h b/src/target/armv4_5_cache.h
index 03b9593527014cc0c3283a2d48f44b8d61fd252c..2fd1ca3873e332a7478dcddbe14422d426ef899e 100644 (file)
--- a/src/target/armv4_5_cache.h
+++ b/src/target/armv4_5_cache.h
@@ -13,45 +13,43 @@
  *   GNU General Public License for more details.                          *
  *                                                                         *
  *   You should have received a copy of the GNU General Public License     *
- *   along with this program; if not, write to the                         *
- *   Free Software Foundation, Inc.,                                       *
- *   59 Temple Place - Suite 330, Boston, MA  02111-1307, USA.             *
+ *   along with this program.  If not, see <http://www.gnu.org/licenses/>. *
  ***************************************************************************/
-#ifndef ARMV4_5_CACHE_H
-#define ARMV4_5_CACHE_H
 
-#include "types.h"
-#include "command.h"
+#ifndef OPENOCD_TARGET_ARMV4_5_CACHE_H
+#define OPENOCD_TARGET_ARMV4_5_CACHE_H
 
-typedef struct armv4_5_cachesize_s
-{
+struct command_context;
+
+struct armv4_5_cachesize {
        int linelen;
        int associativity;
        int nsets;
        int cachesize;
-} armv4_5_cachesize_t;
+};
 
-typedef struct armv4_5_cache_common_s
-{
+struct armv4_5_cache_common {
        int ctype;      /* specify supported cache operations */
        int separate;   /* separate caches or unified cache */
-       armv4_5_cachesize_t d_u_size;   /* data cache */
-       armv4_5_cachesize_t i_size; /* instruction cache */
+       struct armv4_5_cachesize d_u_size;      /* data cache */
+       struct armv4_5_cachesize i_size; /* instruction cache */
        int i_cache_enabled;
        int d_u_cache_enabled;
-} armv4_5_cache_common_t;
+};
 
-extern int armv4_5_identify_cache(u32 cache_type_reg, armv4_5_cache_common_t *cache);
-extern int armv4_5_cache_state(u32 cp15_control_reg, armv4_5_cache_common_t *cache);
+int armv4_5_identify_cache(uint32_t cache_type_reg,
+               struct armv4_5_cache_common *cache);
+int armv4_5_cache_state(uint32_t cp15_control_reg,
+               struct armv4_5_cache_common *cache);
 
-extern int armv4_5_handle_cache_info_command(struct command_context_s *cmd_ctx, armv4_5_cache_common_t *armv4_5_cache);
+int armv4_5_handle_cache_info_command(struct command_context *cmd_ctx,
+               struct armv4_5_cache_common *armv4_5_cache);
 
-enum
-{
+enum {
        ARMV4_5_D_U_CACHE_ENABLED = 0x4,
        ARMV4_5_I_CACHE_ENABLED = 0x1000,
        ARMV4_5_WRITE_BUFFER_ENABLED = 0x8,
        ARMV4_5_CACHE_RR_BIT = 0x5000,
 };
 
-#endif /* ARMV4_5_CACHE_H */
+#endif /* OPENOCD_TARGET_ARMV4_5_CACHE_H */