ARM: rename ARMV4_5_STATE_* as ARM_STATE_*

[openocd.git] / src / target / armv4_5.h

diff --git a/src/target/armv4_5.h b/src/target/armv4_5.h
index a9599c82ba97272622e46ce15afd2c71a41b415d..de1b9333b552b38bd99bd00ae4cdf278f8faf322 100644 (file)
--- a/src/target/armv4_5.h
+++ b/src/target/armv4_5.h
@@ -26,7 +26,9 @@
 #ifndef ARMV4_5_H
 #define ARMV4_5_H
 
-#include "target.h"
+#include <target/target.h>
+#include <helper/command.h>
+
 
 typedef enum armv4_5_mode
 {
@@ -49,9 +51,9 @@ enum armv4_5_mode armv4_5_number_to_mode(int number);
 
 typedef enum armv4_5_state
 {
-       ARMV4_5_STATE_ARM,
-       ARMV4_5_STATE_THUMB,
-       ARMV4_5_STATE_JAZELLE,
+       ARM_STATE_ARM,
+       ARM_STATE_THUMB,
+       ARM_STATE_JAZELLE,
        ARM_STATE_THUMB_EE,
 } armv4_5_state_t;
 
@@ -67,9 +69,6 @@ enum { ARMV4_5_CPSR = 31, };
 
 #define ARMV4_5_COMMON_MAGIC 0x0A450A45
 
-/* NOTE:  this is being morphed into a generic toplevel holder for ARMs. */
-#define armv4_5_common_s arm
-
 /**
  * Represents a generic ARM core, with standard application registers.
  *
@@ -104,14 +103,41 @@ struct arm
        /** Flag reporting unavailability of the BKPT instruction. */
        bool is_armv4;
 
+       /** Flag reporting whether semihosting is active. */
+       bool is_semihosting;
+
+       /** Value to be returned by semihosting SYS_ERRNO request. */
+       int semihosting_errno;
+
+       /** Backpointer to the target. */
+       struct target *target;
+
+       /** Handle for the debug module, if one is present. */
+       struct arm_dpm *dpm;
+
        /** Handle for the Embedded Trace Module, if one is present. */
        struct etm_context *etm;
 
+       /* FIXME all these methods should take "struct arm *" not target */
+
        int (*full_context)(struct target *target);
        int (*read_core_reg)(struct target *target, struct reg *reg,
                        int num, enum armv4_5_mode mode);
        int (*write_core_reg)(struct target *target, struct reg *reg,
                        int num, enum armv4_5_mode mode, uint32_t value);
+
+       /** Read coprocessor register.  */
+       int (*mrc)(struct target *target, int cpnum,
+                       uint32_t op1, uint32_t op2,
+                       uint32_t CRn, uint32_t CRm,
+                       uint32_t *value);
+
+       /* Write coprocessor register.  */
+       int (*mcr)(struct target *target, int cpnum,
+                       uint32_t op1, uint32_t op2,
+                       uint32_t CRn, uint32_t CRm,
+                       uint32_t value);
+
        void *arch_info;
 };
 
@@ -152,7 +178,8 @@ int armv4_5_arch_state(struct target *target);
 int armv4_5_get_gdb_reg_list(struct target *target,
                struct reg **reg_list[], int *reg_list_size);
 
-int armv4_5_register_commands(struct command_context *cmd_ctx);
+extern const struct command_registration arm_command_handlers[];
+
 int armv4_5_init_arch_info(struct target *target, struct arm *armv4_5);
 
 int armv4_5_run_algorithm(struct target *target,