ARMV4_5_STATE_ARM,
ARMV4_5_STATE_THUMB,
ARMV4_5_STATE_JAZELLE,
+ ARM_STATE_THUMB_EE,
} armv4_5_state_t;
extern char* armv4_5_state_strings[];
-extern const int armv4_5_core_reg_map[7][17];
+extern const int armv4_5_core_reg_map[8][17];
#define ARMV4_5_CORE_REG_MODE(cache, mode, num) \
cache->reg_list[armv4_5_core_reg_map[armv4_5_mode_to_number(mode)][num]]
ARMV4_5_SPSR_IRQ = 33,
ARMV4_5_SPSR_SVC = 34,
ARMV4_5_SPSR_ABT = 35,
- ARMV4_5_SPSR_UND = 36
+ ARMV4_5_SPSR_UND = 36,
+ ARM_SPSR_MON = 39,
};
#define ARMV4_5_COMMON_MAGIC 0x0A450A45
struct etm_context *etm;
int (*full_context)(struct target *target);
- int (*read_core_reg)(struct target *target,
+ int (*read_core_reg)(struct target *target, struct reg *reg,
int num, enum armv4_5_mode mode);
- int (*write_core_reg)(struct target *target,
+ int (*write_core_reg)(struct target *target, struct reg *reg,
int num, enum armv4_5_mode mode, uint32_t value);
void *arch_info;
};
enum armv4_5_state core_state;
};
-struct armv4_5_core_reg
+struct arm_reg
{
int num;
enum armv4_5_mode mode;
struct target *target;
struct arm *armv4_5_common;
+ uint32_t value;
};
struct reg_cache* armv4_5_build_reg_cache(struct target *target,
uint32_t entry_point, uint32_t exit_point,
int timeout_ms, void *arch_info);
-int armv4_5_invalidate_core_regs(struct target *target);
-
int arm_checksum_memory(struct target *target,
uint32_t address, uint32_t count, uint32_t *checksum);
int arm_blank_check_memory(struct target *target,