* Cortex-M series cores do not support as many core states or shadowed
* registers as traditional ARM cores, and only support Thumb2 instructions.
*/
-typedef struct arm
+struct arm
{
int common_magic;
- reg_cache_t *core_cache;
+ struct reg_cache *core_cache;
int /* armv4_5_mode */ core_mode;
enum armv4_5_state core_state;
bool is_armv4;
/** Handle for the Embedded Trace Module, if one is present. */
- struct etm *etm;
+ struct etm_context *etm;
int (*full_context)(struct target_s *target);
int (*read_core_reg)(struct target_s *target,
int (*write_core_reg)(struct target_s *target,
int num, enum armv4_5_mode mode, uint32_t value);
void *arch_info;
-} armv4_5_common_t;
+};
#define target_to_armv4_5 target_to_arm
return arm && arm->common_magic == ARMV4_5_COMMON_MAGIC;
}
-typedef struct armv4_5_algorithm_s
+struct armv4_5_algorithm
{
int common_magic;
enum armv4_5_mode core_mode;
enum armv4_5_state core_state;
-} armv4_5_algorithm_t;
+};
-typedef struct armv4_5_core_reg_s
+struct armv4_5_core_reg
{
int num;
enum armv4_5_mode mode;
target_t *target;
- armv4_5_common_t *armv4_5_common;
-} armv4_5_core_reg_t;
+ struct arm *armv4_5_common;
+};
-reg_cache_t* armv4_5_build_reg_cache(target_t *target,
- armv4_5_common_t *armv4_5_common);
+struct reg_cache* armv4_5_build_reg_cache(target_t *target,
+ struct arm *armv4_5_common);
/* map psr mode bits to linear number */
static __inline int armv4_5_mode_to_number(enum armv4_5_mode mode)
reg_t **reg_list[], int *reg_list_size);
int armv4_5_register_commands(struct command_context_s *cmd_ctx);
-int armv4_5_init_arch_info(target_t *target, armv4_5_common_t *armv4_5);
+int armv4_5_init_arch_info(target_t *target, struct arm *armv4_5);
int armv4_5_run_algorithm(struct target_s *target,
int num_mem_params, struct mem_param *mem_params,
- int num_reg_params, reg_param_t *reg_params,
+ int num_reg_params, struct reg_param *reg_params,
uint32_t entry_point, uint32_t exit_point,
int timeout_ms, void *arch_info);