ARMV4_5_SPSR_ABT = 35,
ARMV4_5_SPSR_UND = 36,
ARM_SPSR_MON = 41,
+ ARM_SPSR_HYP = 43,
};
static const uint8_t arm_usr_indices[17] = {
39, 40, ARM_SPSR_MON,
};
+static const uint8_t arm_hyp_indices[2] = {
+ 42, ARM_SPSR_HYP,
+};
+
static const struct {
const char *name;
unsigned short psr;
.name = "Handler",
.psr = ARM_MODE_HANDLER,
},
+
+ /* armv7-a with virtualization extension */
+ {
+ .name = "Hypervisor",
+ .psr = ARM_MODE_HYP,
+ .n_indices = ARRAY_SIZE(arm_hyp_indices),
+ .indices = arm_hyp_indices,
+ },
};
/** Map PSR mode bits to the name of an ARM processor operating mode. */
case ARM_MODE_MON:
case ARM_MODE_1176_MON:
return 7;
+ case ARM_MODE_HYP:
+ return 8;
default:
LOG_ERROR("invalid mode value encountered %d", mode);
return -1;
return ARM_MODE_SYS;
case 7:
return ARM_MODE_MON;
+ case 8:
+ return ARM_MODE_HYP;
default:
LOG_ERROR("mode index out of bounds %d", number);
return ARM_MODE_ANY;
[40] = { .name = "lr_mon", .cookie = 14, .mode = ARM_MODE_MON, .gdb_index = 49, },
[41] = { .name = "spsr_mon", .cookie = 16, .mode = ARM_MODE_MON, .gdb_index = 50, },
+ /* These exist only when the Virtualization Extensions is present */
+ [42] = { .name = "sp_hyp", .cookie = 13, .mode = ARM_MODE_HYP, .gdb_index = 51, },
+ [43] = { .name = "spsr_hyp", .cookie = 16, .mode = ARM_MODE_HYP, .gdb_index = 52, },
};
static const struct {
/* map core mode (USR, FIQ, ...) and register number to
* indices into the register cache
*/
-const int armv4_5_core_reg_map[8][17] = {
+const int armv4_5_core_reg_map[9][17] = {
{ /* USR */
0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 31
},
},
{ /* MON */
0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 39, 40, 15, 41,
+ },
+ { /* HYP */
+ 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 42, 14, 15, 43,
}
};
for (i = 0; i < num_core_regs; i++) {
/* Skip registers this core doesn't expose */
if (arm_core_regs[i].mode == ARM_MODE_MON
- && arm->core_type != ARM_MODE_MON)
+ && arm->core_type != ARM_CORE_TYPE_SEC_EXT
+ && arm->core_type != ARM_CORE_TYPE_VIRT_EXT)
+ continue;
+ if (arm_core_regs[i].mode == ARM_MODE_HYP
+ && arm->core_type != ARM_CORE_TYPE_VIRT_EXT)
continue;
/* REVISIT handle Cortex-M, which only shadows R13/SP */
return cache;
}
+void arm_free_reg_cache(struct arm *arm)
+{
+ if (!arm || !arm->core_cache)
+ return;
+
+ struct reg_cache *cache = arm->core_cache;
+
+ for (unsigned int i = 0; i < cache->num_regs; i++) {
+ struct reg *reg = &cache->reg_list[i];
+
+ free(reg->feature);
+ free(reg->reg_data_type);
+ }
+
+ free(cache->reg_list[0].arch_info);
+ free(cache->reg_list);
+ free(cache);
+
+ arm->core_cache = NULL;
+}
+
int arm_arch_state(struct target *target)
{
struct arm *arm = target_to_arm(target);
return ERROR_OK;
}
-#define ARMV4_5_CORE_REG_MODENUM(cache, mode, num) \
- (cache->reg_list[armv4_5_core_reg_map[mode][num]])
-
COMMAND_HANDLER(handle_armv4_5_reg_command)
{
struct target *target = get_current_target(CMD_CTX);
return ERROR_FAIL;
}
- if (arm->core_type != ARM_MODE_ANY) {
+ if (arm->core_type != ARM_CORE_TYPE_STD) {
command_print(CMD,
"Microcontroller Profile not supported - use standard reg cmd");
return ERROR_OK;
char *sep = "\n";
char *shadow = "";
+ if (!arm_mode_data[mode].n_indices)
+ continue;
+
/* label this bank of registers (or shadows) */
switch (arm_mode_data[mode].psr) {
case ARM_MODE_SYS:
name = "System and User";
sep = "";
break;
+ case ARM_MODE_HYP:
+ if (arm->core_type != ARM_CORE_TYPE_VIRT_EXT)
+ continue;
+ /* FALLTHROUGH */
case ARM_MODE_MON:
- if (arm->core_type != ARM_MODE_MON)
+ case ARM_MODE_1176_MON:
+ if (arm->core_type != ARM_CORE_TYPE_SEC_EXT
+ && arm->core_type != ARM_CORE_TYPE_VIRT_EXT)
continue;
/* FALLTHROUGH */
default:
return ERROR_FAIL;
}
- if (arm->core_type == ARM_MODE_THREAD) {
+ if (arm->core_type == ARM_CORE_TYPE_M_PROFILE) {
/* armv7m not supported */
command_print(CMD, "Unsupported Command");
return ERROR_OK;
COMMAND_HANDLER(handle_arm_disassemble_command)
{
- int retval = ERROR_OK;
+#if HAVE_CAPSTONE
struct target *target = get_current_target(CMD_CTX);
if (target == NULL) {
struct arm *arm = target_to_arm(target);
target_addr_t address;
- int count = 1;
- int thumb = 0;
+ unsigned int count = 1;
+ bool thumb = false;
if (!is_arm(arm)) {
command_print(CMD, "current target isn't an ARM");
return ERROR_FAIL;
}
- if (arm->core_type == ARM_MODE_THREAD) {
+ if (arm->core_type == ARM_CORE_TYPE_M_PROFILE) {
/* armv7m is always thumb mode */
- thumb = 1;
+ thumb = true;
}
switch (CMD_ARGC) {
case 3:
if (strcmp(CMD_ARGV[2], "thumb") != 0)
- goto usage;
- thumb = 1;
+ return ERROR_COMMAND_SYNTAX_ERROR;
+ thumb = true;
/* FALL THROUGH */
case 2:
- COMMAND_PARSE_NUMBER(int, CMD_ARGV[1], count);
+ COMMAND_PARSE_NUMBER(uint, CMD_ARGV[1], count);
/* FALL THROUGH */
case 1:
COMMAND_PARSE_ADDRESS(CMD_ARGV[0], address);
if (address & 0x01) {
if (!thumb) {
command_print(CMD, "Disassemble as Thumb");
- thumb = 1;
+ thumb = true;
}
address &= ~1;
}
break;
default:
-usage:
- count = 0;
- retval = ERROR_COMMAND_SYNTAX_ERROR;
- }
-
- while (count-- > 0) {
- struct arm_instruction cur_instruction;
-
- if (thumb) {
- /* Always use Thumb2 disassembly for best handling
- * of 32-bit BL/BLX, and to work with newer cores
- * (some ARMv6, all ARMv7) that use Thumb2.
- */
- retval = thumb2_opcode(target, address,
- &cur_instruction);
- if (retval != ERROR_OK)
- break;
- } else {
- uint32_t opcode;
-
- retval = target_read_u32(target, address, &opcode);
- if (retval != ERROR_OK)
- break;
- retval = arm_evaluate_opcode(opcode, address,
- &cur_instruction) != ERROR_OK;
- if (retval != ERROR_OK)
- break;
- }
- command_print(CMD, "%s", cur_instruction.text);
- address += cur_instruction.instruction_size;
+ return ERROR_COMMAND_SYNTAX_ERROR;
}
- return retval;
+ return arm_disassemble(CMD, target, address, count, thumb);
+#else
+ command_print(CMD, "capstone disassembly framework required");
+ return ERROR_FAIL;
+#endif
}
static int jim_mcrmrc(Jim_Interp *interp, int argc, Jim_Obj * const *argv)
(*reg_list)[25] = arm->cpsr;
return ERROR_OK;
- break;
case REG_CLASS_ALL:
- *reg_list_size = (arm->core_type != ARM_MODE_MON ? 48 : 51);
+ switch (arm->core_type) {
+ case ARM_CORE_TYPE_SEC_EXT:
+ *reg_list_size = 51;
+ break;
+ case ARM_CORE_TYPE_VIRT_EXT:
+ *reg_list_size = 53;
+ break;
+ default:
+ *reg_list_size = 48;
+ }
unsigned int list_size_core = *reg_list_size;
if (arm->arm_vfp_version == ARM_VFP_V3)
*reg_list_size += 33;
for (i = 13; i < ARRAY_SIZE(arm_core_regs); i++) {
int reg_index = arm->core_cache->reg_list[i].number;
- if (!(arm_core_regs[i].mode == ARM_MODE_MON
- && arm->core_type != ARM_MODE_MON))
- (*reg_list)[reg_index] = &(arm->core_cache->reg_list[i]);
+
+ if (arm_core_regs[i].mode == ARM_MODE_MON
+ && arm->core_type != ARM_CORE_TYPE_SEC_EXT
+ && arm->core_type != ARM_CORE_TYPE_VIRT_EXT)
+ continue;
+ if (arm_core_regs[i].mode == ARM_MODE_HYP
+ && arm->core_type != ARM_CORE_TYPE_VIRT_EXT)
+ continue;
+ (*reg_list)[reg_index] = &(arm->core_cache->reg_list[i]);
}
/* When we supply the target description, there is no need for fake FPA */
}
return ERROR_OK;
- break;
default:
LOG_ERROR("not a valid register class type in query.");
return ERROR_FAIL;
- break;
}
}
arm->common_magic = ARM_COMMON_MAGIC;
/* core_type may be overridden by subtype logic */
- if (arm->core_type != ARM_MODE_THREAD) {
- arm->core_type = ARM_MODE_ANY;
+ if (arm->core_type != ARM_CORE_TYPE_M_PROFILE) {
+ arm->core_type = ARM_CORE_TYPE_STD;
arm_set_cpsr(arm, ARM_MODE_USR);
}
Code Review / openocd.git / blobdiff