#include "register.h"
-static const char *armv4_5_core_reg_list[] =
-{
- "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7",
- "r8", "r9", "r10", "r11", "r12", "r13_usr", "lr_usr", "pc",
+/* offsets into armv4_5 core register cache */
+enum {
+// ARMV4_5_CPSR = 31,
+ ARMV4_5_SPSR_FIQ = 32,
+ ARMV4_5_SPSR_IRQ = 33,
+ ARMV4_5_SPSR_SVC = 34,
+ ARMV4_5_SPSR_ABT = 35,
+ ARMV4_5_SPSR_UND = 36,
+ ARM_SPSR_MON = 39,
+};
- "r8_fiq", "r9_fiq", "r10_fiq", "r11_fiq", "r12_fiq", "r13_fiq", "lr_fiq",
+static const uint8_t arm_usr_indices[17] = {
+ 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, ARMV4_5_CPSR,
+};
- "r13_irq", "lr_irq",
+static const uint8_t arm_fiq_indices[8] = {
+ 16, 17, 18, 19, 20, 21, 22, ARMV4_5_SPSR_FIQ,
+};
- "r13_svc", "lr_svc",
+static const uint8_t arm_irq_indices[3] = {
+ 23, 24, ARMV4_5_SPSR_IRQ,
+};
- "r13_abt", "lr_abt",
+static const uint8_t arm_svc_indices[3] = {
+ 25, 26, ARMV4_5_SPSR_SVC,
+};
- "r13_und", "lr_und",
+static const uint8_t arm_abt_indices[3] = {
+ 27, 28, ARMV4_5_SPSR_ABT,
+};
- "cpsr", "spsr_fiq", "spsr_irq", "spsr_svc", "spsr_abt", "spsr_und",
+static const uint8_t arm_und_indices[3] = {
+ 29, 30, ARMV4_5_SPSR_UND,
+};
- "r13_mon", "lr_mon", "spsr_mon",
+static const uint8_t arm_mon_indices[3] = {
+ 37, 38, ARM_SPSR_MON,
};
static const struct {
const char *name;
- unsigned psr;
+ unsigned short psr;
+ /* For user and system modes, these list indices for all registers.
+ * otherwise they're just indices for the shadow registers and SPSR.
+ */
+ unsigned short n_indices;
+ const uint8_t *indices;
} arm_mode_data[] = {
/* Seven modes are standard from ARM7 on. "System" and "User" share
* the same registers; other modes shadow from 3 to 8 registers.
{
.name = "User",
.psr = ARMV4_5_MODE_USR,
+ .n_indices = ARRAY_SIZE(arm_usr_indices),
+ .indices = arm_usr_indices,
},
{
.name = "FIQ",
.psr = ARMV4_5_MODE_FIQ,
+ .n_indices = ARRAY_SIZE(arm_fiq_indices),
+ .indices = arm_fiq_indices,
},
{
.name = "Supervisor",
.psr = ARMV4_5_MODE_SVC,
+ .n_indices = ARRAY_SIZE(arm_svc_indices),
+ .indices = arm_svc_indices,
},
{
.name = "Abort",
.psr = ARMV4_5_MODE_ABT,
+ .n_indices = ARRAY_SIZE(arm_abt_indices),
+ .indices = arm_abt_indices,
},
{
.name = "IRQ",
.psr = ARMV4_5_MODE_IRQ,
+ .n_indices = ARRAY_SIZE(arm_irq_indices),
+ .indices = arm_irq_indices,
},
{
- .name = "Undefined" /* instruction */,
+ .name = "Undefined instruction",
.psr = ARMV4_5_MODE_UND,
+ .n_indices = ARRAY_SIZE(arm_und_indices),
+ .indices = arm_und_indices,
},
{
.name = "System",
.psr = ARMV4_5_MODE_SYS,
+ .n_indices = ARRAY_SIZE(arm_usr_indices),
+ .indices = arm_usr_indices,
},
/* TrustZone "Security Extensions" add a secure monitor mode.
* This is distinct from a "debug monitor" which can support
{
.name = "Secure Monitor",
.psr = ARM_MODE_MON,
+ .n_indices = ARRAY_SIZE(arm_mon_indices),
+ .indices = arm_mon_indices,
},
};
char* armv4_5_state_strings[] =
{
- "ARM", "Thumb", "Jazelle"
+ "ARM", "Thumb", "Jazelle", "ThumbEE",
};
-static const struct armv4_5_core_reg armv4_5_core_reg_list_arch_info[] =
-{
- {0, ARMV4_5_MODE_ANY, NULL, NULL},
- {1, ARMV4_5_MODE_ANY, NULL, NULL},
- {2, ARMV4_5_MODE_ANY, NULL, NULL},
- {3, ARMV4_5_MODE_ANY, NULL, NULL},
- {4, ARMV4_5_MODE_ANY, NULL, NULL},
- {5, ARMV4_5_MODE_ANY, NULL, NULL},
- {6, ARMV4_5_MODE_ANY, NULL, NULL},
- {7, ARMV4_5_MODE_ANY, NULL, NULL},
- {8, ARMV4_5_MODE_ANY, NULL, NULL},
- {9, ARMV4_5_MODE_ANY, NULL, NULL},
- {10, ARMV4_5_MODE_ANY, NULL, NULL},
- {11, ARMV4_5_MODE_ANY, NULL, NULL},
- {12, ARMV4_5_MODE_ANY, NULL, NULL},
- {13, ARMV4_5_MODE_USR, NULL, NULL},
- {14, ARMV4_5_MODE_USR, NULL, NULL},
- {15, ARMV4_5_MODE_ANY, NULL, NULL},
-
- {8, ARMV4_5_MODE_FIQ, NULL, NULL},
- {9, ARMV4_5_MODE_FIQ, NULL, NULL},
- {10, ARMV4_5_MODE_FIQ, NULL, NULL},
- {11, ARMV4_5_MODE_FIQ, NULL, NULL},
- {12, ARMV4_5_MODE_FIQ, NULL, NULL},
- {13, ARMV4_5_MODE_FIQ, NULL, NULL},
- {14, ARMV4_5_MODE_FIQ, NULL, NULL},
-
- {13, ARMV4_5_MODE_IRQ, NULL, NULL},
- {14, ARMV4_5_MODE_IRQ, NULL, NULL},
-
- {13, ARMV4_5_MODE_SVC, NULL, NULL},
- {14, ARMV4_5_MODE_SVC, NULL, NULL},
-
- {13, ARMV4_5_MODE_ABT, NULL, NULL},
- {14, ARMV4_5_MODE_ABT, NULL, NULL},
-
- {13, ARMV4_5_MODE_UND, NULL, NULL},
- {14, ARMV4_5_MODE_UND, NULL, NULL},
-
- {16, ARMV4_5_MODE_ANY, NULL, NULL},
- {16, ARMV4_5_MODE_FIQ, NULL, NULL},
- {16, ARMV4_5_MODE_IRQ, NULL, NULL},
- {16, ARMV4_5_MODE_SVC, NULL, NULL},
- {16, ARMV4_5_MODE_ABT, NULL, NULL},
- {16, ARMV4_5_MODE_UND, NULL, NULL},
-
- {13, ARM_MODE_MON, NULL, NULL},
- {14, ARM_MODE_MON, NULL, NULL},
- {16, ARM_MODE_MON, NULL, NULL},
+/* Templates for ARM core registers.
+ *
+ * NOTE: offsets in this table are coupled to the arm_mode_data
+ * table above, the armv4_5_core_reg_map array below, and also to
+ * the ARMV4_5_CPSR symbol (which should vanish after ARM11 updates).
+ */
+static const struct {
+ /* The name is used for e.g. the "regs" command. */
+ const char *name;
+
+ /* The {cookie, mode} tuple uniquely identifies one register.
+ * In a given mode, cookies 0..15 map to registers R0..R15,
+ * with R13..R15 usually called SP, LR, PC.
+ *
+ * MODE_ANY is used as *input* to the mapping, and indicates
+ * various special cases (sigh) and errors.
+ *
+ * Cookie 16 is (currently) confusing, since it indicates
+ * CPSR -or- SPSR depending on whether 'mode' is MODE_ANY.
+ * (Exception modes have both CPSR and SPSR registers ...)
+ */
+ unsigned cookie;
+ enum armv4_5_mode mode;
+} arm_core_regs[] = {
+ /* IMPORTANT: we guarantee that the first eight cached registers
+ * correspond to r0..r7, and the fifteenth to PC, so that callers
+ * don't need to map them.
+ */
+ { .name = "r0", .cookie = 0, .mode = ARMV4_5_MODE_ANY, },
+ { .name = "r1", .cookie = 1, .mode = ARMV4_5_MODE_ANY, },
+ { .name = "r2", .cookie = 2, .mode = ARMV4_5_MODE_ANY, },
+ { .name = "r3", .cookie = 3, .mode = ARMV4_5_MODE_ANY, },
+ { .name = "r4", .cookie = 4, .mode = ARMV4_5_MODE_ANY, },
+ { .name = "r5", .cookie = 5, .mode = ARMV4_5_MODE_ANY, },
+ { .name = "r6", .cookie = 6, .mode = ARMV4_5_MODE_ANY, },
+ { .name = "r7", .cookie = 7, .mode = ARMV4_5_MODE_ANY, },
+
+ /* NOTE: regs 8..12 might be shadowed by FIQ ... flagging
+ * them as MODE_ANY creates special cases. (ANY means
+ * "not mapped" elsewhere; here it's "everything but FIQ".)
+ */
+ { .name = "r8", .cookie = 8, .mode = ARMV4_5_MODE_ANY, },
+ { .name = "r9", .cookie = 9, .mode = ARMV4_5_MODE_ANY, },
+ { .name = "r10", .cookie = 10, .mode = ARMV4_5_MODE_ANY, },
+ { .name = "r11", .cookie = 11, .mode = ARMV4_5_MODE_ANY, },
+ { .name = "r12", .cookie = 12, .mode = ARMV4_5_MODE_ANY, },
+
+ /* NOTE all MODE_USR registers are equivalent to MODE_SYS ones */
+ { .name = "sp_usr", .cookie = 13, .mode = ARMV4_5_MODE_USR, },
+ { .name = "lr_usr", .cookie = 14, .mode = ARMV4_5_MODE_USR, },
+
+ /* guaranteed to be at index 15 */
+ { .name = "pc", .cookie = 15, .mode = ARMV4_5_MODE_ANY, },
+
+ { .name = "r8_fiq", .cookie = 8, .mode = ARMV4_5_MODE_FIQ, },
+ { .name = "r9_fiq", .cookie = 9, .mode = ARMV4_5_MODE_FIQ, },
+ { .name = "r10_fiq", .cookie = 10, .mode = ARMV4_5_MODE_FIQ, },
+ { .name = "r11_fiq", .cookie = 11, .mode = ARMV4_5_MODE_FIQ, },
+ { .name = "r12_fiq", .cookie = 12, .mode = ARMV4_5_MODE_FIQ, },
+
+ { .name = "lr_fiq", .cookie = 13, .mode = ARMV4_5_MODE_FIQ, },
+ { .name = "sp_fiq", .cookie = 14, .mode = ARMV4_5_MODE_FIQ, },
+
+ { .name = "lr_irq", .cookie = 13, .mode = ARMV4_5_MODE_IRQ, },
+ { .name = "sp_irq", .cookie = 14, .mode = ARMV4_5_MODE_IRQ, },
+
+ { .name = "lr_svc", .cookie = 13, .mode = ARMV4_5_MODE_SVC, },
+ { .name = "sp_svc", .cookie = 14, .mode = ARMV4_5_MODE_SVC, },
+
+ { .name = "lr_abt", .cookie = 13, .mode = ARMV4_5_MODE_ABT, },
+ { .name = "sp_abt", .cookie = 14, .mode = ARMV4_5_MODE_ABT, },
+
+ { .name = "lr_und", .cookie = 13, .mode = ARMV4_5_MODE_UND, },
+ { .name = "sp_und", .cookie = 14, .mode = ARMV4_5_MODE_UND, },
+
+ { .name = "cpsr", .cookie = 16, .mode = ARMV4_5_MODE_ANY, },
+ { .name = "spsr_fiq", .cookie = 16, .mode = ARMV4_5_MODE_FIQ, },
+ { .name = "spsr_irq", .cookie = 16, .mode = ARMV4_5_MODE_IRQ, },
+ { .name = "spsr_svc", .cookie = 16, .mode = ARMV4_5_MODE_SVC, },
+ { .name = "spsr_abt", .cookie = 16, .mode = ARMV4_5_MODE_ABT, },
+ { .name = "spsr_und", .cookie = 16, .mode = ARMV4_5_MODE_UND, },
+
+ { .name = "lr_mon", .cookie = 13, .mode = ARM_MODE_MON, },
+ { .name = "sp_mon", .cookie = 14, .mode = ARM_MODE_MON, },
+ { .name = "spsr_mon", .cookie = 16, .mode = ARM_MODE_MON, },
};
-/* map core mode (USR, FIQ, ...) and register number to indizes into the register cache */
+/* map core mode (USR, FIQ, ...) and register number to
+ * indices into the register cache
+ */
const int armv4_5_core_reg_map[8][17] =
{
{ /* USR */
}
};
+/**
+ * Configures host-side ARM records to reflect the specified CPSR.
+ * Later, code can use arm_reg_current() to map register numbers
+ * according to how they are exposed by this mode.
+ */
+void arm_set_cpsr(struct arm *arm, uint32_t cpsr)
+{
+ enum armv4_5_mode mode = cpsr & 0x1f;
+ int num;
+
+ /* NOTE: this may be called very early, before the register
+ * cache is set up. We can't defend against many errors, in
+ * particular against CPSRs that aren't valid *here* ...
+ */
+ if (arm->cpsr) {
+ buf_set_u32(arm->cpsr->value, 0, 32, cpsr);
+ arm->cpsr->valid = 1;
+ arm->cpsr->dirty = 0;
+ }
+
+ arm->core_mode = mode;
+
+ /* mode_to_number() warned; set up a somewhat-sane mapping */
+ num = armv4_5_mode_to_number(mode);
+ if (num < 0) {
+ mode = ARMV4_5_MODE_USR;
+ num = 0;
+ }
+
+ arm->map = &armv4_5_core_reg_map[num][0];
+ arm->spsr = (mode == ARMV4_5_MODE_USR || mode == ARMV4_5_MODE_SYS)
+ ? NULL
+ : arm->core_cache->reg_list + arm->map[16];
+
+ /* Older ARMs won't have the J bit */
+ enum armv4_5_state state;
+
+ if (cpsr & (1 << 5)) { /* T */
+ if (cpsr & (1 << 24)) { /* J */
+ LOG_WARNING("ThumbEE -- incomplete support");
+ state = ARM_STATE_THUMB_EE;
+ } else
+ state = ARMV4_5_STATE_THUMB;
+ } else {
+ if (cpsr & (1 << 24)) { /* J */
+ LOG_ERROR("Jazelle state handling is BROKEN!");
+ state = ARMV4_5_STATE_JAZELLE;
+ } else
+ state = ARMV4_5_STATE_ARM;
+ }
+ arm->core_state = state;
+
+ LOG_DEBUG("set CPSR %#8.8x: %s mode, %s state", (unsigned) cpsr,
+ arm_mode_name(mode),
+ armv4_5_state_strings[arm->core_state]);
+}
+
+/**
+ * Returns handle to the register currently mapped to a given number.
+ * Someone must have called arm_set_cpsr() before.
+ *
+ * \param arm This core's state and registers are used.
+ * \param regnum From 0..15 corresponding to R0..R14 and PC.
+ * Note that R0..R7 don't require mapping; you may access those
+ * as the first eight entries in the register cache. Likewise
+ * R15 (PC) doesn't need mapping; you may also access it directly.
+ * However, R8..R14, and SPSR (arm->spsr) *must* be mapped.
+ * CPSR (arm->cpsr) is also not mapped.
+ */
+struct reg *arm_reg_current(struct arm *arm, unsigned regnum)
+{
+ struct reg *r;
+
+ if (regnum > 16)
+ return NULL;
+
+ r = arm->core_cache->reg_list + arm->map[regnum];
+
+ /* e.g. invalid CPSR said "secure monitor" mode on a core
+ * that doesn't support it...
+ */
+ if (!r) {
+ LOG_ERROR("Invalid CPSR mode");
+ r = arm->core_cache->reg_list + regnum;
+ }
+
+ return r;
+}
+
static const uint8_t arm_gdb_dummy_fp_value[12];
/**
static int armv4_5_get_core_reg(struct reg *reg)
{
int retval;
- struct armv4_5_core_reg *armv4_5 = reg->arch_info;
+ struct arm_reg *armv4_5 = reg->arch_info;
struct target *target = armv4_5->target;
if (target->state != TARGET_HALTED)
return ERROR_TARGET_NOT_HALTED;
}
- retval = armv4_5->armv4_5_common->read_core_reg(target, armv4_5->num, armv4_5->mode);
- if (retval == ERROR_OK)
+ retval = armv4_5->armv4_5_common->read_core_reg(target, reg, armv4_5->num, armv4_5->mode);
+ if (retval == ERROR_OK) {
reg->valid = 1;
+ reg->dirty = 0;
+ }
return retval;
}
static int armv4_5_set_core_reg(struct reg *reg, uint8_t *buf)
{
- struct armv4_5_core_reg *armv4_5 = reg->arch_info;
+ struct arm_reg *armv4_5 = reg->arch_info;
struct target *target = armv4_5->target;
- struct armv4_5_common_s *armv4_5_target = target_to_armv4_5(target);
+ struct arm *armv4_5_target = target_to_armv4_5(target);
uint32_t value = buf_get_u32(buf, 0, 32);
if (target->state != TARGET_HALTED)
return ERROR_TARGET_NOT_HALTED;
}
- if (reg == &armv4_5_target->core_cache->reg_list[ARMV4_5_CPSR])
- {
- if (value & 0x20)
- {
- /* T bit should be set */
- if (armv4_5_target->core_state == ARMV4_5_STATE_ARM)
- {
- /* change state to Thumb */
- LOG_DEBUG("changing to Thumb state");
- armv4_5_target->core_state = ARMV4_5_STATE_THUMB;
- }
- }
- else
- {
- /* T bit should be cleared */
- if (armv4_5_target->core_state == ARMV4_5_STATE_THUMB)
- {
- /* change state to ARM */
- LOG_DEBUG("changing to ARM state");
- armv4_5_target->core_state = ARMV4_5_STATE_ARM;
- }
- }
-
- if (armv4_5_target->core_mode != (enum armv4_5_mode)(value & 0x1f))
- {
+ /* Except for CPSR, the "reg" command exposes a writeback model
+ * for the register cache.
+ */
+ if (reg == armv4_5_target->cpsr) {
+ arm_set_cpsr(armv4_5_target, value);
+
+ /* Older cores need help to be in ARM mode during halt
+ * mode debug, so we clear the J and T bits if we flush.
+ * For newer cores (v6/v7a/v7r) we don't need that, but
+ * it won't hurt since CPSR is always flushed anyway.
+ */
+ if (armv4_5_target->core_mode !=
+ (enum armv4_5_mode)(value & 0x1f)) {
LOG_DEBUG("changing ARM core mode to '%s'",
arm_mode_name(value & 0x1f));
- armv4_5_target->core_mode = value & 0x1f;
- armv4_5_target->write_core_reg(target, 16, ARMV4_5_MODE_ANY, value);
+ value &= ~((1 << 24) | (1 << 5));
+ armv4_5_target->write_core_reg(target, reg,
+ 16, ARMV4_5_MODE_ANY, value);
}
+ } else {
+ buf_set_u32(reg->value, 0, 32, value);
+ reg->valid = 1;
}
-
- buf_set_u32(reg->value, 0, 32, value);
reg->dirty = 1;
- reg->valid = 1;
return ERROR_OK;
}
.set = armv4_5_set_core_reg,
};
-/** Marks the contents of the register cache as invalid (and clean). */
-int armv4_5_invalidate_core_regs(struct target *target)
-{
- struct armv4_5_common_s *armv4_5 = target_to_armv4_5(target);
- unsigned num_regs = armv4_5->core_cache->num_regs;
- struct reg *reg = armv4_5->core_cache->reg_list;
-
- for (unsigned i = 0; i < num_regs; i++, reg++) {
- reg->valid = 0;
- reg->dirty = 0;
- }
-
- /* FIXME don't bother returning a value then */
- return ERROR_OK;
-}
-
struct reg_cache* armv4_5_build_reg_cache(struct target *target, struct arm *armv4_5_common)
{
- int num_regs = ARRAY_SIZE(armv4_5_core_reg_list_arch_info);
+ int num_regs = ARRAY_SIZE(arm_core_regs);
struct reg_cache *cache = malloc(sizeof(struct reg_cache));
struct reg *reg_list = calloc(num_regs, sizeof(struct reg));
- struct armv4_5_core_reg *arch_info = calloc(num_regs,
- sizeof(struct armv4_5_core_reg));
+ struct arm_reg *arch_info = calloc(num_regs, sizeof(struct arm_reg));
int i;
if (!cache || !reg_list || !arch_info) {
for (i = 0; i < num_regs; i++)
{
/* Skip registers this core doesn't expose */
- if (armv4_5_core_reg_list_arch_info[i].mode == ARM_MODE_MON
+ if (arm_core_regs[i].mode == ARM_MODE_MON
&& armv4_5_common->core_type != ARM_MODE_MON)
continue;
/* REVISIT handle Cortex-M, which only shadows R13/SP */
- arch_info[i] = armv4_5_core_reg_list_arch_info[i];
+ arch_info[i].num = arm_core_regs[i].cookie;
+ arch_info[i].mode = arm_core_regs[i].mode;
arch_info[i].target = target;
arch_info[i].armv4_5_common = armv4_5_common;
- reg_list[i].name = (char *) armv4_5_core_reg_list[i];
+
+ reg_list[i].name = (char *) arm_core_regs[i].name;
reg_list[i].size = 32;
- reg_list[i].value = calloc(1, 4);
+ reg_list[i].value = &arch_info[i].value;
reg_list[i].type = &arm_reg_type;
reg_list[i].arch_info = &arch_info[i];
cache->num_regs++;
}
+ armv4_5_common->cpsr = reg_list + ARMV4_5_CPSR;
+ armv4_5_common->core_cache = cache;
return cache;
}
int armv4_5_arch_state(struct target *target)
{
- struct armv4_5_common_s *armv4_5 = target_to_armv4_5(target);
+ struct arm *armv4_5 = target_to_armv4_5(target);
if (armv4_5->common_magic != ARMV4_5_COMMON_MAGIC)
{
armv4_5_state_strings[armv4_5->core_state],
Jim_Nvp_value2name_simple(nvp_target_debug_reason, target->debug_reason)->name,
arm_mode_name(armv4_5->core_mode),
- buf_get_u32(armv4_5->core_cache->reg_list[ARMV4_5_CPSR].value, 0, 32),
+ buf_get_u32(armv4_5->cpsr->value, 0, 32),
buf_get_u32(armv4_5->core_cache->reg_list[15].value, 0, 32));
return ERROR_OK;
COMMAND_HANDLER(handle_armv4_5_reg_command)
{
- char output[128];
- int output_len;
- int mode, num;
struct target *target = get_current_target(CMD_CTX);
- struct armv4_5_common_s *armv4_5 = target_to_armv4_5(target);
+ struct arm *armv4_5 = target_to_armv4_5(target);
+ unsigned num_regs;
+ struct reg *regs;
if (!is_arm(armv4_5))
{
if (target->state != TARGET_HALTED)
{
command_print(CMD_CTX, "error: target must be halted for register accesses");
- return ERROR_OK;
+ return ERROR_FAIL;
}
if (!is_arm_mode(armv4_5->core_mode))
return ERROR_FAIL;
}
- for (num = 0; num <= 15; num++)
- {
- output_len = 0;
- for (mode = 0; mode < 6; mode++)
- {
- if (!ARMV4_5_CORE_REG_MODENUM(armv4_5->core_cache, mode, num).valid)
- {
- armv4_5->full_context(target);
- }
- output_len += snprintf(output + output_len,
- 128 - output_len,
+ num_regs = armv4_5->core_cache->num_regs;
+ regs = armv4_5->core_cache->reg_list;
+
+ for (unsigned mode = 0; mode < ARRAY_SIZE(arm_mode_data); mode++) {
+ const char *name;
+ char *sep = "\n";
+ char *shadow = "";
+
+ /* label this bank of registers (or shadows) */
+ switch (arm_mode_data[mode].psr) {
+ case ARMV4_5_MODE_SYS:
+ continue;
+ case ARMV4_5_MODE_USR:
+ name = "System and User";
+ sep = "";
+ break;
+ case ARM_MODE_MON:
+ if (armv4_5->core_type != ARM_MODE_MON)
+ continue;
+ /* FALLTHROUGH */
+ default:
+ name = arm_mode_data[mode].name;
+ shadow = "shadow ";
+ break;
+ }
+ command_print(CMD_CTX, "%s%s mode %sregisters",
+ sep, name, shadow);
+
+ /* display N rows of up to 4 registers each */
+ for (unsigned i = 0; i < arm_mode_data[mode].n_indices;) {
+ char output[80];
+ int output_len = 0;
+
+ for (unsigned j = 0; j < 4; j++, i++) {
+ uint32_t value;
+ struct reg *reg = regs;
+
+ if (i >= arm_mode_data[mode].n_indices)
+ break;
+
+ reg += arm_mode_data[mode].indices[i];
+
+ /* REVISIT be smarter about faults... */
+ if (!reg->valid)
+ armv4_5->full_context(target);
+
+ value = buf_get_u32(reg->value, 0, 32);
+ output_len += snprintf(output + output_len,
+ sizeof(output) - output_len,
"%8s: %8.8" PRIx32 " ",
- ARMV4_5_CORE_REG_MODENUM(armv4_5->core_cache, mode, num).name,
- buf_get_u32(ARMV4_5_CORE_REG_MODENUM(armv4_5->core_cache, mode, num).value, 0, 32));
+ reg->name, value);
+ }
+ command_print(CMD_CTX, "%s", output);
}
- command_print(CMD_CTX, "%s", output);
}
- command_print(CMD_CTX,
- " cpsr: %8.8" PRIx32 " spsr_fiq: %8.8" PRIx32 " spsr_irq: %8.8" PRIx32 " spsr_svc: %8.8" PRIx32 " spsr_abt: %8.8" PRIx32 " spsr_und: %8.8" PRIx32 "",
- buf_get_u32(armv4_5->core_cache->reg_list[ARMV4_5_CPSR].value, 0, 32),
- buf_get_u32(armv4_5->core_cache->reg_list[ARMV4_5_SPSR_FIQ].value, 0, 32),
- buf_get_u32(armv4_5->core_cache->reg_list[ARMV4_5_SPSR_IRQ].value, 0, 32),
- buf_get_u32(armv4_5->core_cache->reg_list[ARMV4_5_SPSR_SVC].value, 0, 32),
- buf_get_u32(armv4_5->core_cache->reg_list[ARMV4_5_SPSR_ABT].value, 0, 32),
- buf_get_u32(armv4_5->core_cache->reg_list[ARMV4_5_SPSR_UND].value, 0, 32));
return ERROR_OK;
}
COMMAND_HANDLER(handle_armv4_5_core_state_command)
{
struct target *target = get_current_target(CMD_CTX);
- struct armv4_5_common_s *armv4_5 = target_to_armv4_5(target);
+ struct arm *armv4_5 = target_to_armv4_5(target);
if (!is_arm(armv4_5))
{
return retval;
}
-int armv4_5_register_commands(struct command_context *cmd_ctx)
-{
- struct command *armv4_5_cmd;
-
- armv4_5_cmd = register_command(cmd_ctx, NULL, "arm",
- NULL, COMMAND_ANY,
- "generic ARM commands");
-
- register_command(cmd_ctx, armv4_5_cmd, "reg",
- handle_armv4_5_reg_command, COMMAND_EXEC,
- "display ARM core registers");
- register_command(cmd_ctx, armv4_5_cmd, "core_state",
- handle_armv4_5_core_state_command, COMMAND_EXEC,
- "display/change ARM core state <arm | thumb>");
- register_command(cmd_ctx, armv4_5_cmd, "disassemble",
- handle_armv4_5_disassemble_command, COMMAND_EXEC,
- "disassemble instructions "
- "<address> [<count> ['thumb']]");
-
- return ERROR_OK;
-}
+static const struct command_registration arm_exec_command_handlers[] = {
+ {
+ .name = "reg",
+ .handler = &handle_armv4_5_reg_command,
+ .mode = COMMAND_EXEC,
+ .help = "display ARM core registers",
+ },
+ {
+ .name = "core_state",
+ .handler = &handle_armv4_5_core_state_command,
+ .mode = COMMAND_EXEC,
+ .usage = "<arm | thumb>",
+ .help = "display/change ARM core state",
+ },
+ {
+ .name = "disassemble",
+ .handler = &handle_armv4_5_disassemble_command,
+ .mode = COMMAND_EXEC,
+ .usage = "<address> [<count> ['thumb']]",
+ .help = "disassemble instructions ",
+ },
+ COMMAND_REGISTRATION_DONE
+};
+const struct command_registration arm_command_handlers[] = {
+ {
+ .name = "arm",
+ .mode = COMMAND_ANY,
+ .help = "ARM command group",
+ .chain = arm_exec_command_handlers,
+ },
+ COMMAND_REGISTRATION_DONE
+};
int armv4_5_get_gdb_reg_list(struct target *target, struct reg **reg_list[], int *reg_list_size)
{
- struct armv4_5_common_s *armv4_5 = target_to_armv4_5(target);
+ struct arm *armv4_5 = target_to_armv4_5(target);
int i;
if (!is_arm_mode(armv4_5->core_mode))
*reg_list = malloc(sizeof(struct reg*) * (*reg_list_size));
for (i = 0; i < 16; i++)
- {
- (*reg_list)[i] = &ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5->core_mode, i);
- }
+ (*reg_list)[i] = arm_reg_current(armv4_5, i);
for (i = 16; i < 24; i++)
- {
(*reg_list)[i] = &arm_gdb_dummy_fp_reg;
- }
(*reg_list)[24] = &arm_gdb_dummy_fps_reg;
- (*reg_list)[25] = &armv4_5->core_cache->reg_list[ARMV4_5_CPSR];
+ (*reg_list)[25] = armv4_5->cpsr;
return ERROR_OK;
}
static int armv4_5_run_algorithm_completion(struct target *target, uint32_t exit_point, int timeout_ms, void *arch_info)
{
int retval;
- struct armv4_5_common_s *armv4_5 = target_to_armv4_5(target);
+ struct arm *armv4_5 = target_to_armv4_5(target);
if ((retval = target_wait_state(target, TARGET_HALTED, timeout_ms)) != ERROR_OK)
{
return ERROR_OK;
}
-int armv4_5_run_algorithm_inner(struct target *target, int num_mem_params, struct mem_param *mem_params, int num_reg_params, struct reg_param *reg_params, uint32_t entry_point, uint32_t exit_point, int timeout_ms, void *arch_info, int (*run_it)(struct target *target, uint32_t exit_point, int timeout_ms, void *arch_info))
+int armv4_5_run_algorithm_inner(struct target *target,
+ int num_mem_params, struct mem_param *mem_params,
+ int num_reg_params, struct reg_param *reg_params,
+ uint32_t entry_point, uint32_t exit_point,
+ int timeout_ms, void *arch_info,
+ int (*run_it)(struct target *target, uint32_t exit_point,
+ int timeout_ms, void *arch_info))
{
- struct armv4_5_common_s *armv4_5 = target_to_armv4_5(target);
+ struct arm *armv4_5 = target_to_armv4_5(target);
struct armv4_5_algorithm *armv4_5_algorithm_info = arch_info;
enum armv4_5_state core_state = armv4_5->core_state;
- enum armv4_5_mode core_mode = armv4_5->core_mode;
uint32_t context[17];
uint32_t cpsr;
int exit_breakpoint_size = 0;
int i;
int retval = ERROR_OK;
+
LOG_DEBUG("Running algorithm");
if (armv4_5_algorithm_info->common_magic != ARMV4_5_COMMON_MAGIC)
return ERROR_FAIL;
}
+ /* save r0..pc, cpsr-or-spsr, and then cpsr-for-sure;
+ * they'll be restored later.
+ */
for (i = 0; i <= 16; i++)
{
- if (!ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5_algorithm_info->core_mode, i).valid)
- armv4_5->read_core_reg(target, i, armv4_5_algorithm_info->core_mode);
- context[i] = buf_get_u32(ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5_algorithm_info->core_mode, i).value, 0, 32);
+ struct reg *r;
+
+ r = &ARMV4_5_CORE_REG_MODE(armv4_5->core_cache,
+ armv4_5_algorithm_info->core_mode, i);
+ if (!r->valid)
+ armv4_5->read_core_reg(target, r, i,
+ armv4_5_algorithm_info->core_mode);
+ context[i] = buf_get_u32(r->value, 0, 32);
}
- cpsr = buf_get_u32(armv4_5->core_cache->reg_list[ARMV4_5_CPSR].value, 0, 32);
+ cpsr = buf_get_u32(armv4_5->cpsr->value, 0, 32);
for (i = 0; i < num_mem_params; i++)
{
if (armv4_5_algorithm_info->core_mode != ARMV4_5_MODE_ANY)
{
- LOG_DEBUG("setting core_mode: 0x%2.2x", armv4_5_algorithm_info->core_mode);
- buf_set_u32(armv4_5->core_cache->reg_list[ARMV4_5_CPSR].value, 0, 5, armv4_5_algorithm_info->core_mode);
- armv4_5->core_cache->reg_list[ARMV4_5_CPSR].dirty = 1;
- armv4_5->core_cache->reg_list[ARMV4_5_CPSR].valid = 1;
+ LOG_DEBUG("setting core_mode: 0x%2.2x",
+ armv4_5_algorithm_info->core_mode);
+ buf_set_u32(armv4_5->cpsr->value, 0, 5,
+ armv4_5_algorithm_info->core_mode);
+ armv4_5->cpsr->dirty = 1;
+ armv4_5->cpsr->valid = 1;
}
/* terminate using a hardware or (ARMv5+) software breakpoint */
}
}
+ /* restore everything we saved before (17 or 18 registers) */
for (i = 0; i <= 16; i++)
{
uint32_t regvalue;
ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5_algorithm_info->core_mode, i).dirty = 1;
}
}
- buf_set_u32(armv4_5->core_cache->reg_list[ARMV4_5_CPSR].value, 0, 32, cpsr);
- armv4_5->core_cache->reg_list[ARMV4_5_CPSR].valid = 1;
- armv4_5->core_cache->reg_list[ARMV4_5_CPSR].dirty = 1;
+
+ arm_set_cpsr(armv4_5, cpsr);
+ armv4_5->cpsr->dirty = 1;
armv4_5->core_state = core_state;
- armv4_5->core_mode = core_mode;
return retval;
}
static int arm_full_context(struct target *target)
{
- struct armv4_5_common_s *armv4_5 = target_to_armv4_5(target);
+ struct arm *armv4_5 = target_to_armv4_5(target);
unsigned num_regs = armv4_5->core_cache->num_regs;
struct reg *reg = armv4_5->core_cache->reg_list;
int retval = ERROR_OK;
int armv4_5_init_arch_info(struct target *target, struct arm *armv4_5)
{
target->arch_info = armv4_5;
+ armv4_5->target = target;
armv4_5->common_magic = ARMV4_5_COMMON_MAGIC;
- armv4_5->core_state = ARMV4_5_STATE_ARM;
- armv4_5->core_mode = ARMV4_5_MODE_USR;
+ arm_set_cpsr(armv4_5, ARMV4_5_MODE_USR);
/* core_type may be overridden by subtype logic */
armv4_5->core_type = ARMV4_5_MODE_ANY;
Code Review / openocd.git / blobdiff