unsigned cookie;
enum armv4_5_mode mode;
} arm_core_regs[] = {
+ /* IMPORTANT: we guarantee that the first eight cached registers
+ * correspond to r0..r7, and the fifteenth to PC, so that callers
+ * don't need to map them.
+ */
{ .name = "r0", .cookie = 0, .mode = ARMV4_5_MODE_ANY, },
{ .name = "r1", .cookie = 1, .mode = ARMV4_5_MODE_ANY, },
{ .name = "r2", .cookie = 2, .mode = ARMV4_5_MODE_ANY, },
{ .name = "r7", .cookie = 7, .mode = ARMV4_5_MODE_ANY, },
/* NOTE: regs 8..12 might be shadowed by FIQ ... flagging
- * them as MODE_ANY creates special cases.
+ * them as MODE_ANY creates special cases. (ANY means
+ * "not mapped" elsewhere; here it's "everything but FIQ".)
*/
{ .name = "r8", .cookie = 8, .mode = ARMV4_5_MODE_ANY, },
{ .name = "r9", .cookie = 9, .mode = ARMV4_5_MODE_ANY, },
{ .name = "sp_usr", .cookie = 13, .mode = ARMV4_5_MODE_USR, },
{ .name = "lr_usr", .cookie = 14, .mode = ARMV4_5_MODE_USR, },
+ /* guaranteed to be at index 15 */
{ .name = "pc", .cookie = 15, .mode = ARMV4_5_MODE_ANY, },
{ .name = "r8_fiq", .cookie = 8, .mode = ARMV4_5_MODE_FIQ, },
}
};
+/**
+ * Configures host-side ARM records to reflect the specified CPSR.
+ * Later, code can use arm_reg_current() to map register numbers
+ * according to how they are exposed by this mode.
+ */
+void arm_set_cpsr(struct arm *arm, uint32_t cpsr)
+{
+ enum armv4_5_mode mode = cpsr & 0x1f;
+ int num;
+
+ /* NOTE: this may be called very early, before the register
+ * cache is set up. We can't defend against many errors, in
+ * particular against CPSRs that aren't valid *here* ...
+ */
+ if (arm->cpsr) {
+ buf_set_u32(arm->cpsr->value, 0, 32, cpsr);
+ arm->cpsr->valid = 1;
+ arm->cpsr->dirty = 0;
+ }
+
+ arm->core_mode = mode;
+
+ /* mode_to_number() warned; set up a somewhat-sane mapping */
+ num = armv4_5_mode_to_number(mode);
+ if (num < 0) {
+ mode = ARMV4_5_MODE_USR;
+ num = 0;
+ }
+
+ arm->map = &armv4_5_core_reg_map[num][0];
+ arm->spsr = (mode == ARMV4_5_MODE_USR || mode == ARMV4_5_MODE_SYS)
+ ? NULL
+ : arm->core_cache->reg_list + arm->map[16];
+
+ /* Older ARMs won't have the J bit */
+ enum armv4_5_state state;
+
+ if (cpsr & (1 << 5)) { /* T */
+ if (cpsr & (1 << 24)) { /* J */
+ LOG_WARNING("ThumbEE -- incomplete support");
+ state = ARM_STATE_THUMB_EE;
+ } else
+ state = ARMV4_5_STATE_THUMB;
+ } else {
+ if (cpsr & (1 << 24)) { /* J */
+ LOG_ERROR("Jazelle state handling is BROKEN!");
+ state = ARMV4_5_STATE_JAZELLE;
+ } else
+ state = ARMV4_5_STATE_ARM;
+ }
+ arm->core_state = state;
+}
+
+/**
+ * Returns handle to the register currently mapped to a given number.
+ * Someone must have called arm_set_cpsr() before.
+ *
+ * \param arm This core's state and registers are used.
+ * \param regnum From 0..15 corresponding to R0..R14 and PC.
+ * Note that R0..R7 don't require mapping; you may access those
+ * as the first eight entries in the register cache. Likewise
+ * R15 (PC) doesn't need mapping; you may also access it directly.
+ * However, R8..R14, and SPSR (arm->spsr) *must* be mapped.
+ * CPSR (arm->cpsr) is also not mapped.
+ */
+struct reg *arm_reg_current(struct arm *arm, unsigned regnum)
+{
+ struct reg *r;
+
+ if (regnum > 16)
+ return NULL;
+
+ r = arm->core_cache->reg_list + arm->map[regnum];
+
+ /* e.g. invalid CPSR said "secure monitor" mode on a core
+ * that doesn't support it...
+ */
+ if (!r) {
+ LOG_ERROR("Invalid CPSR mode");
+ r = arm->core_cache->reg_list + regnum;
+ }
+
+ return r;
+}
+
static const uint8_t arm_gdb_dummy_fp_value[12];
/**
{
struct arm_reg *armv4_5 = reg->arch_info;
struct target *target = armv4_5->target;
- struct armv4_5_common_s *armv4_5_target = target_to_armv4_5(target);
+ struct arm *armv4_5_target = target_to_armv4_5(target);
uint32_t value = buf_get_u32(buf, 0, 32);
if (target->state != TARGET_HALTED)
/* Except for CPSR, the "reg" command exposes a writeback model
* for the register cache.
*/
- buf_set_u32(reg->value, 0, 32, value);
- reg->dirty = 1;
- reg->valid = 1;
-
- if (reg == armv4_5_target->cpsr)
- {
- /* FIXME handle J bit too; mostly for ThumbEE, also Jazelle */
- if (value & 0x20)
- {
- /* T bit should be set */
- if (armv4_5_target->core_state == ARMV4_5_STATE_ARM)
- {
- /* change state to Thumb */
- LOG_DEBUG("changing to Thumb state");
- armv4_5_target->core_state = ARMV4_5_STATE_THUMB;
- }
- }
- else
- {
- /* T bit should be cleared */
- if (armv4_5_target->core_state == ARMV4_5_STATE_THUMB)
- {
- /* change state to ARM */
- LOG_DEBUG("changing to ARM state");
- armv4_5_target->core_state = ARMV4_5_STATE_ARM;
- }
- }
+ if (reg == armv4_5_target->cpsr) {
+ arm_set_cpsr(armv4_5_target, value);
- /* REVISIT Why only update core for mode change, not also
- * for state changes? Possibly older cores need to stay
- * in ARM mode during halt mode debug, not execute Thumb;
- * v6/v7a/v7r seem to do that automatically...
+ /* Older cores need help to be in ARM mode during halt
+ * mode debug, so we clear the J and T bits if we flush.
+ * For newer cores (v6/v7a/v7r) we don't need that, but
+ * it won't hurt since CPSR is always flushed anyway.
*/
-
- if (armv4_5_target->core_mode != (enum armv4_5_mode)(value & 0x1f))
- {
+ if (armv4_5_target->core_mode !=
+ (enum armv4_5_mode)(value & 0x1f)) {
LOG_DEBUG("changing ARM core mode to '%s'",
arm_mode_name(value & 0x1f));
- armv4_5_target->core_mode = value & 0x1f;
+ value &= ~((1 << 24) | (1 << 5));
armv4_5_target->write_core_reg(target, reg,
16, ARMV4_5_MODE_ANY, value);
- reg->dirty = 0;
}
+ } else {
+ buf_set_u32(reg->value, 0, 32, value);
+ reg->valid = 1;
}
+ reg->dirty = 1;
return ERROR_OK;
}
int armv4_5_arch_state(struct target *target)
{
- struct armv4_5_common_s *armv4_5 = target_to_armv4_5(target);
+ struct arm *armv4_5 = target_to_armv4_5(target);
if (armv4_5->common_magic != ARMV4_5_COMMON_MAGIC)
{
COMMAND_HANDLER(handle_armv4_5_reg_command)
{
struct target *target = get_current_target(CMD_CTX);
- struct armv4_5_common_s *armv4_5 = target_to_armv4_5(target);
+ struct arm *armv4_5 = target_to_armv4_5(target);
unsigned num_regs;
struct reg *regs;
COMMAND_HANDLER(handle_armv4_5_core_state_command)
{
struct target *target = get_current_target(CMD_CTX);
- struct armv4_5_common_s *armv4_5 = target_to_armv4_5(target);
+ struct arm *armv4_5 = target_to_armv4_5(target);
if (!is_arm(armv4_5))
{
return retval;
}
-int armv4_5_register_commands(struct command_context *cmd_ctx)
-{
- struct command *armv4_5_cmd;
-
- armv4_5_cmd = register_command(cmd_ctx, NULL, "arm",
- NULL, COMMAND_ANY,
- "generic ARM commands");
-
- register_command(cmd_ctx, armv4_5_cmd, "reg",
- handle_armv4_5_reg_command, COMMAND_EXEC,
- "display ARM core registers");
- register_command(cmd_ctx, armv4_5_cmd, "core_state",
- handle_armv4_5_core_state_command, COMMAND_EXEC,
- "display/change ARM core state <arm | thumb>");
- register_command(cmd_ctx, armv4_5_cmd, "disassemble",
- handle_armv4_5_disassemble_command, COMMAND_EXEC,
- "disassemble instructions "
- "<address> [<count> ['thumb']]");
-
- return ERROR_OK;
-}
+static const struct command_registration arm_exec_command_handlers[] = {
+ {
+ .name = "reg",
+ .handler = &handle_armv4_5_reg_command,
+ .mode = COMMAND_EXEC,
+ .help = "display ARM core registers",
+ },
+ {
+ .name = "core_state",
+ .handler = &handle_armv4_5_core_state_command,
+ .mode = COMMAND_EXEC,
+ .usage = "<arm | thumb>",
+ .help = "display/change ARM core state",
+ },
+ {
+ .name = "disassemble",
+ .handler = &handle_armv4_5_disassemble_command,
+ .mode = COMMAND_EXEC,
+ .usage = "<address> [<count> ['thumb']]",
+ .help = "disassemble instructions ",
+ },
+ COMMAND_REGISTRATION_DONE
+};
+const struct command_registration arm_command_handlers[] = {
+ {
+ .name = "arm",
+ .mode = COMMAND_ANY,
+ .help = "ARM command group",
+ .chain = arm_exec_command_handlers,
+ },
+ COMMAND_REGISTRATION_DONE
+};
int armv4_5_get_gdb_reg_list(struct target *target, struct reg **reg_list[], int *reg_list_size)
{
- struct armv4_5_common_s *armv4_5 = target_to_armv4_5(target);
+ struct arm *armv4_5 = target_to_armv4_5(target);
int i;
if (!is_arm_mode(armv4_5->core_mode))
*reg_list = malloc(sizeof(struct reg*) * (*reg_list_size));
for (i = 0; i < 16; i++)
- {
- (*reg_list)[i] = &ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5->core_mode, i);
- }
+ (*reg_list)[i] = arm_reg_current(armv4_5, i);
for (i = 16; i < 24; i++)
- {
(*reg_list)[i] = &arm_gdb_dummy_fp_reg;
- }
(*reg_list)[24] = &arm_gdb_dummy_fps_reg;
(*reg_list)[25] = armv4_5->cpsr;
static int armv4_5_run_algorithm_completion(struct target *target, uint32_t exit_point, int timeout_ms, void *arch_info)
{
int retval;
- struct armv4_5_common_s *armv4_5 = target_to_armv4_5(target);
+ struct arm *armv4_5 = target_to_armv4_5(target);
if ((retval = target_wait_state(target, TARGET_HALTED, timeout_ms)) != ERROR_OK)
{
int armv4_5_run_algorithm_inner(struct target *target, int num_mem_params, struct mem_param *mem_params, int num_reg_params, struct reg_param *reg_params, uint32_t entry_point, uint32_t exit_point, int timeout_ms, void *arch_info, int (*run_it)(struct target *target, uint32_t exit_point, int timeout_ms, void *arch_info))
{
- struct armv4_5_common_s *armv4_5 = target_to_armv4_5(target);
+ struct arm *armv4_5 = target_to_armv4_5(target);
struct armv4_5_algorithm *armv4_5_algorithm_info = arch_info;
enum armv4_5_state core_state = armv4_5->core_state;
- enum armv4_5_mode core_mode = armv4_5->core_mode;
uint32_t context[17];
uint32_t cpsr;
int exit_breakpoint_size = 0;
return ERROR_FAIL;
}
+ /* save r0..pc, cpsr-or-spsr, and then cpsr-for-sure;
+ * they'll be restored later.
+ */
for (i = 0; i <= 16; i++)
{
struct reg *r;
}
}
+ /* restore everything we saved before (17 or 18 registers) */
for (i = 0; i <= 16; i++)
{
uint32_t regvalue;
ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5_algorithm_info->core_mode, i).dirty = 1;
}
}
- buf_set_u32(armv4_5->cpsr->value, 0, 32, cpsr);
- armv4_5->cpsr->valid = 1;
+
+ arm_set_cpsr(armv4_5, cpsr);
armv4_5->cpsr->dirty = 1;
armv4_5->core_state = core_state;
- armv4_5->core_mode = core_mode;
return retval;
}
static int arm_full_context(struct target *target)
{
- struct armv4_5_common_s *armv4_5 = target_to_armv4_5(target);
+ struct arm *armv4_5 = target_to_armv4_5(target);
unsigned num_regs = armv4_5->core_cache->num_regs;
struct reg *reg = armv4_5->core_cache->reg_list;
int retval = ERROR_OK;
int armv4_5_init_arch_info(struct target *target, struct arm *armv4_5)
{
target->arch_info = armv4_5;
+ armv4_5->target = target;
armv4_5->common_magic = ARMV4_5_COMMON_MAGIC;
- armv4_5->core_state = ARMV4_5_STATE_ARM;
- armv4_5->core_mode = ARMV4_5_MODE_USR;
+ arm_set_cpsr(armv4_5, ARMV4_5_MODE_USR);
/* core_type may be overridden by subtype logic */
armv4_5->core_type = ARMV4_5_MODE_ANY;
Code Review / openocd.git / blobdiff