- Fixes '+' whitespace

[openocd.git] / src / target / armv4_5.c

diff --git a/src/target/armv4_5.c b/src/target/armv4_5.c
index 1144c7f12508f5636dd9756b292e838336fe937c..33f1a5183b20027a92236a9d85435da3008a2054 100644 (file)
--- a/src/target/armv4_5.c
+++ b/src/target/armv4_5.c
@@ -27,21 +27,10 @@
 #include "config.h"
 #endif
 
-#include "replacements.h"
-
-#include "arm_disassembler.h"
-
 #include "armv4_5.h"
-
-#include "target.h"
-#include "register.h"
-#include "log.h"
+#include "arm_disassembler.h"
 #include "binarybuffer.h"
-#include "command.h"
 
-#include <stdlib.h>
-#include <string.h>
-#include <unistd.h>
 
 bitfield_desc_t armv4_5_psr_bitfield_desc[] =
 {
@@ -82,7 +71,7 @@ char * armv4_5_mode_strings_list[] =
 };
 
 /* Hack! Yuk! allow -1 index, which simplifies codepaths elsewhere in the code */
-char** armv4_5_mode_strings = armv4_5_mode_strings_list+1;
+char** armv4_5_mode_strings = armv4_5_mode_strings_list + 1;
 
 char* armv4_5_state_strings[] =
 {
@@ -164,14 +153,14 @@ int armv4_5_core_reg_map[7][17] =
        }
 };
 
-u8 armv4_5_gdb_dummy_fp_value[] = {0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0};
+uint8_t armv4_5_gdb_dummy_fp_value[] = {0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0};
 
 reg_t armv4_5_gdb_dummy_fp_reg =
 {
        "GDB dummy floating-point register", armv4_5_gdb_dummy_fp_value, 0, 1, 96, NULL, 0, NULL, 0
 };
 
-u8 armv4_5_gdb_dummy_fps_value[] = {0, 0, 0, 0};
+uint8_t armv4_5_gdb_dummy_fps_value[] = {0, 0, 0, 0};
 
 reg_t armv4_5_gdb_dummy_fps_reg =
 {
@@ -196,12 +185,12 @@ int armv4_5_get_core_reg(reg_t *reg)
        return retval;
 }
 
-int armv4_5_set_core_reg(reg_t *reg, u8 *buf)
+int armv4_5_set_core_reg(reg_t *reg, uint8_t *buf)
 {
        armv4_5_core_reg_t *armv4_5 = reg->arch_info;
        target_t *target = armv4_5->target;
        armv4_5_common_t *armv4_5_target = target->arch_info;
-       u32 value = buf_get_u32(buf, 0, 32);
+       uint32_t value = buf_get_u32(buf, 0, 32);
 
        if (target->state != TARGET_HALTED)
        {
@@ -308,7 +297,7 @@ int armv4_5_arch_state(struct target_s *target)
                exit(-1);
        }
 
-       LOG_USER("target halted in %s state due to %s, current mode: %s\ncpsr: 0x%8.8x pc: 0x%8.8x",
+       LOG_USER("target halted in %s state due to %s, current mode: %s\ncpsr: 0x%8.8" PRIx32 " pc: 0x%8.8" PRIx32 "",
                         armv4_5_state_strings[armv4_5->core_state],
                         Jim_Nvp_value2name_simple( nvp_target_debug_reason, target->debug_reason )->name,
                         armv4_5_mode_strings[armv4_5_mode_to_number(armv4_5->core_mode)],
@@ -350,12 +339,16 @@ int handle_armv4_5_reg_command(struct command_context_s *cmd_ctx, char *cmd, cha
                        {
                                armv4_5->full_context(target);
                        }
-                       output_len += snprintf(output + output_len, 128 - output_len, "%8s: %8.8x ", ARMV4_5_CORE_REG_MODENUM(armv4_5->core_cache, mode, num).name,
-                               buf_get_u32(ARMV4_5_CORE_REG_MODENUM(armv4_5->core_cache, mode, num).value, 0, 32));
+                       output_len += snprintf(output + output_len, 
+                                              128 - output_len, 
+                                              "%8s: %8.8" PRIx32 " ", 
+                                              ARMV4_5_CORE_REG_MODENUM(armv4_5->core_cache, mode, num).name,
+                                              buf_get_u32(ARMV4_5_CORE_REG_MODENUM(armv4_5->core_cache, mode, num).value, 0, 32));
                }
-               command_print(cmd_ctx, output);
+               command_print(cmd_ctx, "%s", output);
        }
-       command_print(cmd_ctx, "    cpsr: %8.8x spsr_fiq: %8.8x spsr_irq: %8.8x spsr_svc: %8.8x spsr_abt: %8.8x spsr_und: %8.8x",
+       command_print(cmd_ctx,
+                     "    cpsr: %8.8" PRIx32 " spsr_fiq: %8.8" PRIx32 " spsr_irq: %8.8" PRIx32 " spsr_svc: %8.8" PRIx32 " spsr_abt: %8.8" PRIx32 " spsr_und: %8.8" PRIx32 "",
                          buf_get_u32(armv4_5->core_cache->reg_list[ARMV4_5_CPSR].value, 0, 32),
                          buf_get_u32(armv4_5->core_cache->reg_list[ARMV4_5_SPSR_FIQ].value, 0, 32),
                          buf_get_u32(armv4_5->core_cache->reg_list[ARMV4_5_SPSR_IRQ].value, 0, 32),
@@ -399,12 +392,12 @@ int handle_armv4_5_disassemble_command(struct command_context_s *cmd_ctx, char *
        int retval = ERROR_OK;
        target_t *target = get_current_target(cmd_ctx);
        armv4_5_common_t *armv4_5 = target->arch_info;
-       u32 address;
+       uint32_t address;
        int count;
        int i;
        arm_instruction_t cur_instruction;
-       u32 opcode;
-       u16 thumb_opcode;
+       uint32_t opcode;
+       uint16_t thumb_opcode;
        int thumb = 0;
 
        if (armv4_5->common_magic != ARMV4_5_COMMON_MAGIC)
@@ -497,7 +490,7 @@ int armv4_5_get_gdb_reg_list(target_t *target, reg_t **reg_list[], int *reg_list
 }
 
 /* wait for execution to complete and check exit point */
-static int armv4_5_run_algorithm_completion(struct target_s *target, u32 exit_point, int timeout_ms, void *arch_info)
+static int armv4_5_run_algorithm_completion(struct target_s *target, uint32_t exit_point, int timeout_ms, void *arch_info)
 {
        int retval;
        armv4_5_common_t *armv4_5 = target->arch_info;
@@ -508,9 +501,9 @@ static int armv4_5_run_algorithm_completion(struct target_s *target, u32 exit_po
        }
        if (target->state != TARGET_HALTED)
        {
-               if ((retval=target_halt(target))!=ERROR_OK)
+               if ((retval = target_halt(target)) != ERROR_OK)
                        return retval;
-               if ((retval=target_wait_state(target, TARGET_HALTED, 500))!=ERROR_OK)
+               if ((retval = target_wait_state(target, TARGET_HALTED, 500)) != ERROR_OK)
                {
                        return retval;
                }
@@ -518,7 +511,7 @@ static int armv4_5_run_algorithm_completion(struct target_s *target, u32 exit_po
        }
        if (buf_get_u32(armv4_5->core_cache->reg_list[15].value, 0, 32) != exit_point)
        {
-               LOG_WARNING("target reentered debug state, but not at the desired exit point: 0x%4.4x",
+               LOG_WARNING("target reentered debug state, but not at the desired exit point: 0x%4.4" PRIx32 "",
                        buf_get_u32(armv4_5->core_cache->reg_list[15].value, 0, 32));
                return ERROR_TARGET_TIMEOUT;
        }
@@ -526,14 +519,14 @@ static int armv4_5_run_algorithm_completion(struct target_s *target, u32 exit_po
        return ERROR_OK;
 }
 
-int armv4_5_run_algorithm_inner(struct target_s *target, int num_mem_params, mem_param_t *mem_params, int num_reg_params, reg_param_t *reg_params, u32 entry_point, u32 exit_point, int timeout_ms, void *arch_info, int (*run_it)(struct target_s *target, u32 exit_point, int timeout_ms, void *arch_info))
+int armv4_5_run_algorithm_inner(struct target_s *target, int num_mem_params, mem_param_t *mem_params, int num_reg_params, reg_param_t *reg_params, uint32_t entry_point, uint32_t exit_point, int timeout_ms, void *arch_info, int (*run_it)(struct target_s *target, uint32_t exit_point, int timeout_ms, void *arch_info))
 {
        armv4_5_common_t *armv4_5 = target->arch_info;
        armv4_5_algorithm_t *armv4_5_algorithm_info = arch_info;
        enum armv4_5_state core_state = armv4_5->core_state;
        enum armv4_5_mode core_mode = armv4_5->core_mode;
-       u32 context[17];
-       u32 cpsr;
+       uint32_t context[17];
+       uint32_t cpsr;
        int exit_breakpoint_size = 0;
        int i;
        int retval = ERROR_OK;
@@ -621,11 +614,11 @@ int armv4_5_run_algorithm_inner(struct target_s *target, int num_mem_params, mem
                return retval;
        }
        int retvaltemp;
-       retval=run_it(target, exit_point, timeout_ms, arch_info);
+       retval = run_it(target, exit_point, timeout_ms, arch_info);
 
        breakpoint_remove(target, exit_point);
 
-       if (retval!=ERROR_OK)
+       if (retval != ERROR_OK)
                return retval;
 
        for (i = 0; i < num_mem_params; i++)
@@ -661,11 +654,11 @@ int armv4_5_run_algorithm_inner(struct target_s *target, int num_mem_params, mem
 
        for (i = 0; i <= 16; i++)
        {
-               u32 regvalue;
+               uint32_t regvalue;
                regvalue = buf_get_u32(ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5_algorithm_info->core_mode, i).value, 0, 32);
                if (regvalue != context[i])
                {
-                       LOG_DEBUG("restoring register %s with value 0x%8.8x", ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5_algorithm_info->core_mode, i).name, context[i]);
+                       LOG_DEBUG("restoring register %s with value 0x%8.8" PRIx32 "", ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5_algorithm_info->core_mode, i).name, context[i]);
                        buf_set_u32(ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5_algorithm_info->core_mode, i).value, 0, 32, context[i]);
                        ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5_algorithm_info->core_mode, i).valid = 1;
                        ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5_algorithm_info->core_mode, i).dirty = 1;
@@ -681,7 +674,7 @@ int armv4_5_run_algorithm_inner(struct target_s *target, int num_mem_params, mem
        return retval;
 }
 
-int armv4_5_run_algorithm(struct target_s *target, int num_mem_params, mem_param_t *mem_params, int num_reg_params, reg_param_t *reg_params, u32 entry_point, u32 exit_point, int timeout_ms, void *arch_info)
+int armv4_5_run_algorithm(struct target_s *target, int num_mem_params, mem_param_t *mem_params, int num_reg_params, reg_param_t *reg_params, uint32_t entry_point, uint32_t exit_point, int timeout_ms, void *arch_info)
 {
        return armv4_5_run_algorithm_inner(target, num_mem_params, mem_params, num_reg_params, reg_params, entry_point, exit_point, timeout_ms, arch_info, armv4_5_run_algorithm_completion);
 }