jtag: jtag_add_ir_scan() now takes a single field

[openocd.git] / src / target / armv4_5.c

diff --git a/src/target/armv4_5.c b/src/target/armv4_5.c
index dce6d6a638136721642997c3d893e2d0e488bc25..1e9a2965e35c92250ace2fd671f2e1e3c497808c 100644 (file)
--- a/src/target/armv4_5.c
+++ b/src/target/armv4_5.c
@@ -577,6 +577,7 @@ struct reg_cache *arm_build_reg_cache(struct target *target, struct arm *arm)
                cache->num_regs++;
        }
 
+       arm->pc = reg_list + 15;
        arm->cpsr = reg_list + ARMV4_5_CPSR;
        arm->core_cache = cache;
        return cache;
@@ -595,12 +596,10 @@ int arm_arch_state(struct target *target)
        LOG_USER("target halted in %s state due to %s, current mode: %s\n"
                        "cpsr: 0x%8.8" PRIx32 " pc: 0x%8.8" PRIx32 "%s",
                        arm_state_strings[armv4_5->core_state],
-                       Jim_Nvp_value2name_simple(nvp_target_debug_reason,
-                                       target->debug_reason)->name,
+                       debug_reason_name(target),
                        arm_mode_name(armv4_5->core_mode),
                        buf_get_u32(armv4_5->cpsr->value, 0, 32),
-                       buf_get_u32(armv4_5->core_cache->reg_list[15].value,
-                                       0, 32),
+                       buf_get_u32(armv4_5->pc->value, 0, 32),
                        armv4_5->is_semihosting ? ", semihosting" : "");
 
        return ERROR_OK;
@@ -628,6 +627,12 @@ COMMAND_HANDLER(handle_armv4_5_reg_command)
                return ERROR_FAIL;
        }
 
+       if (armv4_5->core_type != ARM_MODE_ANY)
+       {
+               command_print(CMD_CTX, "Microcontroller Profile not supported - use standard reg cmd");
+               return ERROR_OK;
+       }
+
        if (!is_arm_mode(armv4_5->core_mode))
                return ERROR_FAIL;
 
@@ -707,6 +712,13 @@ COMMAND_HANDLER(handle_armv4_5_core_state_command)
                return ERROR_FAIL;
        }
 
+       if (armv4_5->core_type == ARM_MODE_THREAD)
+       {
+               /* armv7m not supported */
+               command_print(CMD_CTX, "Unsupported Command");
+               return ERROR_OK;
+       }
+
        if (CMD_ARGC > 0)
        {
                if (strcmp(CMD_ARGV[0], "arm") == 0)
@@ -724,7 +736,7 @@ COMMAND_HANDLER(handle_armv4_5_core_state_command)
        return ERROR_OK;
 }
 
-COMMAND_HANDLER(handle_armv4_5_disassemble_command)
+COMMAND_HANDLER(handle_arm_disassemble_command)
 {
        int retval = ERROR_OK;
        struct target *target = get_current_target(CMD_CTX);
@@ -738,6 +750,12 @@ COMMAND_HANDLER(handle_armv4_5_disassemble_command)
                return ERROR_FAIL;
        }
 
+       if (arm->core_type == ARM_MODE_THREAD)
+       {
+               /* armv7m is always thumb mode */
+               thumb = 1;
+       }
+
        switch (CMD_ARGC) {
        case 3:
                if (strcmp(CMD_ARGV[2], "thumb") != 0)
@@ -926,25 +944,68 @@ static int jim_mcrmrc(Jim_Interp *interp, int argc, Jim_Obj *const *argv)
        return JIM_OK;
 }
 
+COMMAND_HANDLER(handle_arm_semihosting_command)
+{
+       struct target *target = get_current_target(CMD_CTX);
+       struct arm *arm = target ? target_to_arm(target) : NULL;
+
+       if (!is_arm(arm)) {
+               command_print(CMD_CTX, "current target isn't an ARM");
+               return ERROR_FAIL;
+       }
+
+       if (!arm->setup_semihosting)
+       {
+               command_print(CMD_CTX, "semihosting not supported for current target");
+       }
+
+       if (CMD_ARGC > 0)
+       {
+               int semihosting;
+
+               COMMAND_PARSE_ENABLE(CMD_ARGV[0], semihosting);
+
+               if (!target_was_examined(target))
+               {
+                       LOG_ERROR("Target not examined yet");
+                       return ERROR_FAIL;
+               }
+
+               if (arm->setup_semihosting(target, semihosting) != ERROR_OK) {
+                       LOG_ERROR("Failed to Configure semihosting");
+                       return ERROR_FAIL;
+               }
+
+               /* FIXME never let that "catch" be dropped! */
+               arm->is_semihosting = semihosting;
+       }
+
+       command_print(CMD_CTX, "semihosting is %s",
+                       arm->is_semihosting
+                       ? "enabled" : "disabled");
+
+       return ERROR_OK;
+}
+
 static const struct command_registration arm_exec_command_handlers[] = {
        {
                .name = "reg",
-               .handler = &handle_armv4_5_reg_command,
+               .handler = handle_armv4_5_reg_command,
                .mode = COMMAND_EXEC,
                .help = "display ARM core registers",
        },
        {
                .name = "core_state",
-               .handler = &handle_armv4_5_core_state_command,
+               .handler = handle_armv4_5_core_state_command,
                .mode = COMMAND_EXEC,
-               .usage = "<arm | thumb>",
+               .usage = "['arm'|'thumb']",
                .help = "display/change ARM core state",
        },
        {
                .name = "disassemble",
-               .handler = &handle_armv4_5_disassemble_command,
+               .handler = handle_arm_disassemble_command,
                .mode = COMMAND_EXEC,
-               .usage = "<address> [<count> ['thumb']]",
+               .usage = "address [count ['thumb']]",
                .help = "disassemble instructions ",
        },
        {
@@ -960,6 +1021,13 @@ static const struct command_registration arm_exec_command_handlers[] = {
                .help = "read coprocessor register",
                .usage = "cpnum op1 CRn op2 CRm",
        },
+       {
+               "semihosting",
+               .handler = handle_arm_semihosting_command,
+               .mode = COMMAND_EXEC,
+               .usage = "['enable'|'disable']",
+               .help = "activate support for semihosting operations",
+       },
 
        COMMAND_REGISTRATION_DONE
 };
@@ -1019,11 +1087,10 @@ static int armv4_5_run_algorithm_completion(struct target *target, uint32_t exit
        }
 
        /* fast exit: ARMv5+ code can use BKPT */
-       if (exit_point && buf_get_u32(armv4_5->core_cache->reg_list[15].value,
-                               0, 32) != exit_point)
+       if (exit_point && buf_get_u32(armv4_5->pc->value, 0, 32) != exit_point)
        {
                LOG_WARNING("target reentered debug state, but not at the desired exit point: 0x%4.4" PRIx32 "",
-                       buf_get_u32(armv4_5->core_cache->reg_list[15].value, 0, 32));
+                       buf_get_u32(armv4_5->pc->value, 0, 32));
                return ERROR_TARGET_TIMEOUT;
        }
 
@@ -1427,10 +1494,12 @@ int arm_init_arch_info(struct target *target, struct arm *armv4_5)
        armv4_5->target = target;
 
        armv4_5->common_magic = ARM_COMMON_MAGIC;
-       arm_set_cpsr(armv4_5, ARM_MODE_USR);
 
        /* core_type may be overridden by subtype logic */
-       armv4_5->core_type = ARM_MODE_ANY;
+       if (armv4_5->core_type != ARM_MODE_THREAD) {
+               armv4_5->core_type = ARM_MODE_ANY;
+               arm_set_cpsr(armv4_5, ARM_MODE_USR);
+       }
 
        /* default full_context() has no core-specific optimizations */
        if (!armv4_5->full_context && armv4_5->read_core_reg)