update files to correct FSF address

[openocd.git] / src / target / armv4_5.c

diff --git a/src/target/armv4_5.c b/src/target/armv4_5.c
index 633e1c717ff757f46acf545fe0a645260752dda3..10f84d81248f1369e8badd3f9f0c40a723c78b53 100644 (file)
--- a/src/target/armv4_5.c
+++ b/src/target/armv4_5.c
@@ -21,7 +21,7 @@
  *   You should have received a copy of the GNU General Public License     *
  *   along with this program; if not, write to the                         *
  *   Free Software Foundation, Inc.,                                       *
- *   59 Temple Place - Suite 330, Boston, MA  02111-1307, USA.             *
+ *   51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.           *
  ***************************************************************************/
 
 #ifdef HAVE_CONFIG_H
@@ -140,6 +140,21 @@ static const struct {
                .n_indices = ARRAY_SIZE(arm_mon_indices),
                .indices = arm_mon_indices,
        },
+
+       /* These special modes are currently only supported
+        * by ARMv6M and ARMv7M profiles */
+       {
+               .name = "Thread",
+               .psr = ARM_MODE_THREAD,
+       },
+       {
+               .name = "Thread (User)",
+               .psr = ARM_MODE_USER_THREAD,
+       },
+       {
+               .name = "Handler",
+               .psr = ARM_MODE_HANDLER,
+       },
 };
 
 /** Map PSR mode bits to the name of an ARM processor operating mode. */
@@ -1002,13 +1017,13 @@ static const struct command_registration arm_exec_command_handlers[] = {
                .mode = COMMAND_EXEC,
                .jim_handler = &jim_mcrmrc,
                .help = "write coprocessor register",
-               .usage = "cpnum op1 CRn op2 CRm value",
+               .usage = "cpnum op1 CRn CRm op2 value",
        },
        {
                .name = "mrc",
                .jim_handler = &jim_mcrmrc,
                .help = "read coprocessor register",
-               .usage = "cpnum op1 CRn op2 CRm",
+               .usage = "cpnum op1 CRn CRm op2",
        },
        {
                "semihosting",
@@ -1300,7 +1315,7 @@ int arm_checksum_memory(struct target *target,
        uint32_t address, uint32_t count, uint32_t *checksum)
 {
        struct working_area *crc_algorithm;
-       struct arm_algorithm armv4_5_info;
+       struct arm_algorithm arm_algo;
        struct arm *arm = target_to_arm(target);
        struct reg_param reg_params[2];
        int retval;
@@ -1352,9 +1367,9 @@ int arm_checksum_memory(struct target *target,
                        return retval;
        }
 
-       armv4_5_info.common_magic = ARM_COMMON_MAGIC;
-       armv4_5_info.core_mode = ARM_MODE_SVC;
-       armv4_5_info.core_state = ARM_STATE_ARM;
+       arm_algo.common_magic = ARM_COMMON_MAGIC;
+       arm_algo.core_mode = ARM_MODE_SVC;
+       arm_algo.core_state = ARM_STATE_ARM;
 
        init_reg_param(&reg_params[0], "r0", 32, PARAM_IN_OUT);
        init_reg_param(&reg_params[1], "r1", 32, PARAM_OUT);
@@ -1372,7 +1387,7 @@ int arm_checksum_memory(struct target *target,
        retval = target_run_algorithm(target, 0, NULL, 2, reg_params,
                        crc_algorithm->address,
                        exit_var,
-                       timeout, &armv4_5_info);
+                       timeout, &arm_algo);
        if (retval != ERROR_OK) {
                LOG_ERROR("error executing ARM crc algorithm");
                destroy_reg_param(&reg_params[0]);
@@ -1402,7 +1417,7 @@ int arm_blank_check_memory(struct target *target,
 {
        struct working_area *check_algorithm;
        struct reg_param reg_params[3];
-       struct arm_algorithm armv4_5_info;
+       struct arm_algorithm arm_algo;
        struct arm *arm = target_to_arm(target);
        int retval;
        uint32_t i;
@@ -1436,9 +1451,9 @@ int arm_blank_check_memory(struct target *target,
                        return retval;
        }
 
-       armv4_5_info.common_magic = ARM_COMMON_MAGIC;
-       armv4_5_info.core_mode = ARM_MODE_SVC;
-       armv4_5_info.core_state = ARM_STATE_ARM;
+       arm_algo.common_magic = ARM_COMMON_MAGIC;
+       arm_algo.core_mode = ARM_MODE_SVC;
+       arm_algo.core_state = ARM_STATE_ARM;
 
        init_reg_param(&reg_params[0], "r0", 32, PARAM_OUT);
        buf_set_u32(reg_params[0].value, 0, 32, address);
@@ -1456,7 +1471,7 @@ int arm_blank_check_memory(struct target *target,
        retval = target_run_algorithm(target, 0, NULL, 3, reg_params,
                        check_algorithm->address,
                        exit_var,
-                       10000, &armv4_5_info);
+                       10000, &arm_algo);
        if (retval != ERROR_OK) {
                destroy_reg_param(&reg_params[0]);
                destroy_reg_param(&reg_params[1]);