else
return 0;
case 0xd: /* LE */
- if ((cpsr & 0x40000000) &&
- (((cpsr & 0x80000000) && !(cpsr & 0x10000000))
- || (!(cpsr & 0x80000000) && (cpsr & 0x10000000))))
+ if ((cpsr & 0x40000000) ||
+ ((cpsr & 0x80000000) && !(cpsr & 0x10000000))
+ || (!(cpsr & 0x80000000) && (cpsr & 0x10000000)))
return 1;
else
return 0;
{
uint16_t opcode;
- if ((retval = target_read_u16(target, current_pc, &opcode)) != ERROR_OK)
- {
+ retval = target_read_u16(target, current_pc, &opcode);
+ if (retval != ERROR_OK)
return retval;
- }
- if ((retval = thumb_evaluate_opcode(opcode, current_pc, &instruction)) != ERROR_OK)
- {
+ retval = thumb_evaluate_opcode(opcode, current_pc, &instruction);
+ if (retval != ERROR_OK)
return retval;
- }
instruction_size = 2;
/* check condition code (only for branch instructions) */
- if ((!thumb_pass_branch_condition(sim->get_cpsr(sim, 0, 32), opcode)) &&
- (instruction.type == ARM_B))
+ if (instruction.type == ARM_B &&
+ !thumb_pass_branch_condition(sim->get_cpsr(sim, 0, 32), opcode))
{
if (dry_run_pc)
{
return ERROR_OK;
}
+
+ /* Deal with 32-bit BL/BLX */
+ if ((opcode & 0xf800) == 0xf000) {
+ uint32_t high = instruction.info.b_bl_bx_blx.target_address;
+ retval = target_read_u16(target, current_pc+2, &opcode);
+ if (retval != ERROR_OK)
+ return retval;
+ retval = thumb_evaluate_opcode(opcode, current_pc, &instruction);
+ if (retval != ERROR_OK)
+ return retval;
+ instruction.info.b_bl_bx_blx.target_address += high;
+ }
}
/* examine instruction type */
if (dry_run_pc)
{
- *dry_run_pc = target;
+ *dry_run_pc = target & ~1;
return ERROR_OK;
}
else
else if (instruction.type == ARM_BL)
{
uint32_t old_pc = sim->get_reg(sim, 15);
- sim->set_reg_mode(sim, 14, old_pc + 4);
+ int T = (sim->get_state(sim) == ARMV4_5_STATE_THUMB);
+ sim->set_reg_mode(sim, 14, old_pc + 4 + T);
sim->set_reg(sim, 15, target);
}
else if (instruction.type == ARM_BX)
else if (instruction.type == ARM_BLX)
{
uint32_t old_pc = sim->get_reg(sim, 15);
- sim->set_reg_mode(sim, 14, old_pc + 4);
+ int T = (sim->get_state(sim) == ARMV4_5_STATE_THUMB);
+ sim->set_reg_mode(sim, 14, old_pc + 4 + T);
if (target & 0x1)
{
if (dry_run_pc)
{
if (instruction.info.data_proc.Rd == 15)
- {
- *dry_run_pc = Rd;
- return ERROR_OK;
- }
+ *dry_run_pc = Rd & ~1;
else
- {
*dry_run_pc = current_pc + instruction_size;
- }
return ERROR_OK;
}
else
{
+ if (instruction.info.data_proc.Rd == 15) {
+ sim->set_reg_mode(sim, 15, Rd & ~1);
+ if (Rd & 1)
+ sim->set_state(sim, ARMV4_5_STATE_THUMB);
+ else
+ sim->set_state(sim, ARMV4_5_STATE_ARM);
+ return ERROR_OK;
+ }
sim->set_reg_mode(sim, instruction.info.data_proc.Rd, Rd);
LOG_WARNING("no updating of flags yet");
-
- if (instruction.info.data_proc.Rd == 15)
- return ERROR_OK;
}
}
/* compare instructions (CMP, CMN, TST, TEQ) */
if (dry_run_pc)
{
if (instruction.info.load_store.Rd == 15)
- {
- *dry_run_pc = load_value;
- return ERROR_OK;
- }
+ *dry_run_pc = load_value & ~1;
else
- {
*dry_run_pc = current_pc + instruction_size;
- }
-
return ERROR_OK;
}
else
{
sim->set_reg_mode(sim, instruction.info.load_store.Rn, modified_address);
}
- sim->set_reg_mode(sim, instruction.info.load_store.Rd, load_value);
- if (instruction.info.load_store.Rd == 15)
+ if (instruction.info.load_store.Rd == 15) {
+ sim->set_reg_mode(sim, 15, load_value & ~1);
+ if (load_value & 1)
+ sim->set_state(sim, ARMV4_5_STATE_THUMB);
+ else
+ sim->set_state(sim, ARMV4_5_STATE_ARM);
return ERROR_OK;
+ }
+ sim->set_reg_mode(sim, instruction.info.load_store.Rd, load_value);
}
}
/* load multiple instruction */
{
if (instruction.info.load_store_multiple.register_list & 0x8000)
{
- *dry_run_pc = load_values[15];
+ *dry_run_pc = load_values[15] & ~1;
return ERROR_OK;
}
}
{
if (instruction.info.load_store_multiple.register_list & (1 << i))
{
- sim->set_reg_mode(sim, i, load_values[i]);
+ if (i == 15) {
+ uint32_t val = load_values[i];
+ sim->set_reg_mode(sim, i, val & ~1);
+ if (val & 1)
+ sim->set_state(sim, ARMV4_5_STATE_THUMB);
+ else
+ sim->set_state(sim, ARMV4_5_STATE_ARM);
+ } else {
+ sim->set_reg_mode(sim, i, load_values[i]);
+ }
}
}