ARM: rename ARMV4_5_STATE_* as ARM_STATE_*

[openocd.git] / src / target / arm_simulator.c

diff --git a/src/target/arm_simulator.c b/src/target/arm_simulator.c
index 46cd5587311fb116dc43db806d5f5cafefe7fe27..a1ed54c7fc1c7d1b5367d16b4e8931453d809c02 100644 (file)
--- a/src/target/arm_simulator.c
+++ b/src/target/arm_simulator.c
@@ -27,8 +27,9 @@
 #include "armv4_5.h"
 #include "arm_disassembler.h"
 #include "arm_simulator.h"
-#include "log.h"
-#include "binarybuffer.h"
+#include <helper/binarybuffer.h>
+#include "register.h"
+#include <helper/log.h>
 
 
 static uint32_t arm_shift(uint8_t shift, uint32_t Rm,
@@ -134,7 +135,7 @@ static uint32_t arm_shifter_operand(struct arm_sim_interface *sim,
        uint32_t return_value;
        int instruction_size;
 
-       if (sim->get_state(sim) == ARMV4_5_STATE_ARM)
+       if (sim->get_state(sim) == ARM_STATE_ARM)
                instruction_size = 4;
        else
                instruction_size = 2;
@@ -285,7 +286,7 @@ int arm_simulate_step_core(struct target *target,
        int instruction_size;
        int retval = ERROR_OK;
 
-       if (sim->get_state(sim) == ARMV4_5_STATE_ARM)
+       if (sim->get_state(sim) == ARM_STATE_ARM)
        {
                uint32_t opcode;
 
@@ -391,7 +392,7 @@ int arm_simulate_step_core(struct target *target,
                        else if (instruction.type == ARM_BL)
                        {
                                uint32_t old_pc = sim->get_reg(sim, 15);
-                               int T = (sim->get_state(sim) == ARMV4_5_STATE_THUMB);
+                               int T = (sim->get_state(sim) == ARM_STATE_THUMB);
                                sim->set_reg_mode(sim, 14, old_pc + 4 + T);
                                sim->set_reg(sim, 15, target);
                        }
@@ -399,27 +400,27 @@ int arm_simulate_step_core(struct target *target,
                        {
                                if (target & 0x1)
                                {
-                                       sim->set_state(sim, ARMV4_5_STATE_THUMB);
+                                       sim->set_state(sim, ARM_STATE_THUMB);
                                }
                                else
                                {
-                                       sim->set_state(sim, ARMV4_5_STATE_ARM);
+                                       sim->set_state(sim, ARM_STATE_ARM);
                                }
                                sim->set_reg(sim, 15, target & 0xfffffffe);
                        }
                        else if (instruction.type == ARM_BLX)
                        {
                                uint32_t old_pc = sim->get_reg(sim, 15);
-                               int T = (sim->get_state(sim) == ARMV4_5_STATE_THUMB);
+                               int T = (sim->get_state(sim) == ARM_STATE_THUMB);
                                sim->set_reg_mode(sim, 14, old_pc + 4 + T);
 
                                if (target & 0x1)
                                {
-                                       sim->set_state(sim, ARMV4_5_STATE_THUMB);
+                                       sim->set_state(sim, ARM_STATE_THUMB);
                                }
                                else
                                {
-                                       sim->set_state(sim, ARMV4_5_STATE_ARM);
+                                       sim->set_state(sim, ARM_STATE_ARM);
                                }
                                sim->set_reg(sim, 15, target & 0xfffffffe);
                        }
@@ -492,9 +493,9 @@ int arm_simulate_step_core(struct target *target,
                        if (instruction.info.data_proc.Rd == 15) {
                                sim->set_reg_mode(sim, 15, Rd & ~1);
                                if (Rd & 1)
-                                       sim->set_state(sim, ARMV4_5_STATE_THUMB);
+                                       sim->set_state(sim, ARM_STATE_THUMB);
                                else
-                                       sim->set_state(sim, ARMV4_5_STATE_ARM);
+                                       sim->set_state(sim, ARM_STATE_ARM);
                                return ERROR_OK;
                        }
                        sim->set_reg_mode(sim, instruction.info.data_proc.Rd, Rd);
@@ -604,9 +605,9 @@ int arm_simulate_step_core(struct target *target,
                        if (instruction.info.load_store.Rd == 15) {
                                sim->set_reg_mode(sim, 15, load_value & ~1);
                                if (load_value & 1)
-                                       sim->set_state(sim, ARMV4_5_STATE_THUMB);
+                                       sim->set_state(sim, ARM_STATE_THUMB);
                                else
-                                       sim->set_state(sim, ARMV4_5_STATE_ARM);
+                                       sim->set_state(sim, ARM_STATE_ARM);
                                return ERROR_OK;
                        }
                        sim->set_reg_mode(sim, instruction.info.load_store.Rd, load_value);
@@ -683,9 +684,9 @@ int arm_simulate_step_core(struct target *target,
                                                uint32_t val = load_values[i];
                                        sim->set_reg_mode(sim, i, val & ~1);
                                        if (val & 1)
-                                               sim->set_state(sim, ARMV4_5_STATE_THUMB);
+                                               sim->set_state(sim, ARM_STATE_THUMB);
                                        else
-                                               sim->set_state(sim, ARMV4_5_STATE_ARM);
+                                               sim->set_state(sim, ARM_STATE_ARM);
                                        } else {
                                                sim->set_reg_mode(sim, i, load_values[i]);
                                        }
@@ -820,7 +821,7 @@ static uint32_t armv4_5_get_cpsr(struct arm_sim_interface *sim, int pos, int bit
 {
        struct arm *armv4_5 = (struct arm *)sim->user_data;
 
-       return buf_get_u32(armv4_5->core_cache->reg_list[ARMV4_5_CPSR].value, pos, bits);
+       return buf_get_u32(armv4_5->cpsr->value, pos, bits);
 }
 
 static enum armv4_5_state armv4_5_get_state(struct arm_sim_interface *sim)
@@ -849,7 +850,7 @@ static enum armv4_5_mode armv4_5_get_mode(struct arm_sim_interface *sim)
 
 int arm_simulate_step(struct target *target, uint32_t *dry_run_pc)
 {
-       struct armv4_5_common_s *armv4_5 = target_to_armv4_5(target);
+       struct arm *armv4_5 = target_to_armv4_5(target);
        struct arm_sim_interface sim;
 
        sim.user_data = armv4_5;