ARM: rename ARMV4_5_STATE_* as ARM_STATE_*

[openocd.git] / src / target / arm_dpm.c

diff --git a/src/target/arm_dpm.c b/src/target/arm_dpm.c
index b02baa39780afe686250f85dc7fedf347ca11e49..df9bd958f8772ccdfdfce29ab93d8112c6f67b86 100644 (file)
--- a/src/target/arm_dpm.c
+++ b/src/target/arm_dpm.c
@@ -55,7 +55,9 @@ static int dpm_mrc(struct target *target, int cpnum,
        if (retval != ERROR_OK)
                return retval;
 
-       LOG_DEBUG("MRC p%d, %d, r0, c%d, c%d, %d", cpnum, op1, CRn, CRm, op2);
+       LOG_DEBUG("MRC p%d, %d, r0, c%d, c%d, %d", cpnum,
+                       (int) op1, (int) CRn,
+                       (int) CRm, (int) op2);
 
        /* read coprocessor register into R0; return via DCC */
        retval = dpm->instr_read_data_r0(dpm,
@@ -78,7 +80,9 @@ static int dpm_mcr(struct target *target, int cpnum,
        if (retval != ERROR_OK)
                return retval;
 
-       LOG_DEBUG("MCR p%d, %d, r0, c%d, c%d, %d", cpnum, op1, CRn, CRm, op2);
+       LOG_DEBUG("MCR p%d, %d, r0, c%d, c%d, %d", cpnum,
+                       (int) op1, (int) CRn,
+                       (int) CRm, (int) op2);
 
        /* read DCC into r0; then write coprocessor register from R0 */
        retval = dpm->instr_write_data_r0(dpm,
@@ -143,14 +147,14 @@ static int dpm_read_reg(struct arm_dpm *dpm, struct reg *r, unsigned regnum)
                 * is always right except in those broken-by-intent cases.
                 */
                switch (dpm->arm->core_state) {
-               case ARMV4_5_STATE_ARM:
+               case ARM_STATE_ARM:
                        value -= 8;
                        break;
-               case ARMV4_5_STATE_THUMB:
+               case ARM_STATE_THUMB:
                case ARM_STATE_THUMB_EE:
                        value -= 4;
                        break;
-               case ARMV4_5_STATE_JAZELLE:
+               case ARM_STATE_JAZELLE:
                        /* core-specific ... ? */
                        LOG_WARNING("Jazelle PC adjustment unknown");
                        break;
@@ -276,6 +280,7 @@ fail:
  * Writes all modified core registers for all processor modes.  In normal
  * operation this is called on exit from halting debug state.
  *
+ * @param dpm: represents the processor
  * @param bpwp: true ensures breakpoints and watchpoints are set,
  *     false ensures they are cleared
  */
@@ -739,14 +744,14 @@ static int dpm_remove_watchpoint(struct target *target, struct watchpoint *wp)
 void arm_dpm_report_wfar(struct arm_dpm *dpm, uint32_t addr)
 {
        switch (dpm->arm->core_state) {
-       case ARMV4_5_STATE_ARM:
+       case ARM_STATE_ARM:
                addr -= 8;
                break;
-       case ARMV4_5_STATE_THUMB:
+       case ARM_STATE_THUMB:
        case ARM_STATE_THUMB_EE:
                addr -= 4;
                break;
-       case ARMV4_5_STATE_JAZELLE:
+       case ARM_STATE_JAZELLE:
                /* ?? */
                break;
        }