/* Toggles between recorded core mode (USR, SVC, etc) and a temporary one.
* Routines *must* restore the original mode before returning!!
*/
-static int dpm_modeswitch(struct arm_dpm *dpm, enum arm_mode mode)
+int dpm_modeswitch(struct arm_dpm *dpm, enum arm_mode mode)
{
int retval;
uint32_t cpsr;
cpsr = mode;
retval = dpm->instr_write_data_r0(dpm, ARMV4_5_MSR_GP(0, 0xf, 0), cpsr);
+ if (retval != ERROR_OK)
+ return retval;
if (dpm->instr_cpsr_sync)
retval = dpm->instr_cpsr_sync(dpm);
retval = dpm->instr_write_data_r0(dpm,
ARMV4_5_MSR_GP(0, 0xf, regnum & 1),
value);
+ if (retval != ERROR_OK)
+ return retval;
if (regnum == 16 && dpm->instr_cpsr_sync)
retval = dpm->instr_cpsr_sync(dpm);
retval = dpm_maybe_update_bpwp(dpm, bpwp, &dbp->bpwp,
bp ? &bp->set : NULL);
+ if (retval != ERROR_OK)
+ goto done;
}
}
retval = dpm_maybe_update_bpwp(dpm, bpwp, &dwp->bpwp,
wp ? &wp->set : NULL);
+ if (retval != ERROR_OK)
+ goto done;
}
/* NOTE: writes to breakpoint and watchpoint registers might
/* REVISIT error checks */
if (tmode != ARM_MODE_ANY)
+ {
retval = dpm_modeswitch(dpm, tmode);
+ if (retval != ERROR_OK)
+ goto done;
+ }
}
if (r->mode != mode)
continue;
retval = dpm_write_reg(dpm,
&cache->reg_list[i],
regnum);
-
+ if (retval != ERROR_OK)
+ goto done;
}
} while (did_write);
* defined, and must not write it before CPSR.
*/
retval = dpm_modeswitch(dpm, ARM_MODE_ANY);
+ if (retval != ERROR_OK)
+ goto done;
arm->cpsr->dirty = false;
retval = dpm_write_reg(dpm, arm->pc, 15);
+ if (retval != ERROR_OK)
+ goto done;
arm->pc->dirty = false;
/* flush R0 -- it's *very* dirty by now */
retval = dpm_write_reg(dpm, &cache->reg_list[0], 0);
+ if (retval != ERROR_OK)
+ goto done;
cache->reg_list[0].dirty = false;
/* (void) */ dpm->finish(dpm);
int retval;
if (regnum < 0 || regnum > 16)
- return ERROR_INVALID_ARGUMENTS;
+ return ERROR_COMMAND_SYNTAX_ERROR;
if (regnum == 16) {
if (mode != ARM_MODE_ANY)
}
retval = dpm_read_reg(dpm, r, regnum);
+ if (retval != ERROR_OK)
+ goto fail;
/* always clean up, regardless of error */
if (mode != ARM_MODE_ANY)
if (regnum < 0 || regnum > 16)
- return ERROR_INVALID_ARGUMENTS;
+ return ERROR_COMMAND_SYNTAX_ERROR;
if (regnum == 16) {
if (mode != ARM_MODE_ANY)
/* REVISIT error checks */
retval = dpm_modeswitch(dpm, mode);
+ if (retval != ERROR_OK)
+ goto done;
}
if (r->mode != mode)
continue;
retval = dpm_read_reg(dpm,
&cache->reg_list[i],
(r->num == 16) ? 17 : r->num);
-
+ if (retval != ERROR_OK)
+ goto done;
}
} while (did_read);
/* FALL THROUGH */
default:
LOG_ERROR("unsupported {break,watch}point length/alignment");
- return ERROR_INVALID_ARGUMENTS;
+ return ERROR_COMMAND_SYNTAX_ERROR;
}
/* other shared control bits:
xp->control = control;
xp->dirty = true;
- LOG_DEBUG("BPWP: addr %8.8x, control %x, number %d",
+ LOG_DEBUG("BPWP: addr %8.8" PRIx32 ", control %" PRIx32 ", number %d",
xp->address, control, xp->number);
/* hardware is updated in write_dirty_registers() */
int retval = ERROR_TARGET_RESOURCE_NOT_AVAILABLE;
if (bp->length < 2)
- return ERROR_INVALID_ARGUMENTS;
+ return ERROR_COMMAND_SYNTAX_ERROR;
if (!dpm->bpwp_enable)
return retval;
{
struct arm *arm = target_to_arm(target);
struct arm_dpm *dpm = arm->dpm;
- int retval = ERROR_INVALID_ARGUMENTS;
+ int retval = ERROR_COMMAND_SYNTAX_ERROR;
for (unsigned i = 0; i < dpm->nbp; i++) {
if (dpm->dbp[i].bp == bp) {
return retval;
}
-static int dpm_watchpoint_setup(struct arm_dpm *dpm, unsigned index,
+static int dpm_watchpoint_setup(struct arm_dpm *dpm, unsigned index_t,
struct watchpoint *wp)
{
int retval;
- struct dpm_wp *dwp = dpm->dwp + index;
+ struct dpm_wp *dwp = dpm->dwp + index_t;
uint32_t control;
/* this hardware doesn't support data value matching or masking */
}
dwp->bpwp.control = control;
- dpm->dwp[index].wp = wp;
+ dpm->dwp[index_t].wp = wp;
return retval;
}
{
struct arm *arm = target_to_arm(target);
struct arm_dpm *dpm = arm->dpm;
- int retval = ERROR_INVALID_ARGUMENTS;
+ int retval = ERROR_COMMAND_SYNTAX_ERROR;
for (unsigned i = 0; i < dpm->nwp; i++) {
if (dpm->dwp[i].wp == wp) {