Support for AArch32 SIMD/Floating-point registers

[openocd.git] / src / target / arm_dpm.c

diff --git a/src/target/arm_dpm.c b/src/target/arm_dpm.c
index 3b18719a502d6b83dbffa97ab04f38f16ab5b1e3..3e8180c36db8d8d73baf8c4227609432d478903a 100644 (file)
--- a/src/target/arm_dpm.c
+++ b/src/target/arm_dpm.c
@@ -21,6 +21,7 @@
 
 #include "arm.h"
 #include "arm_dpm.h"
+#include "armv8_dpm.h"
 #include <jtag/jtag.h>
 #include "register.h"
 #include "breakpoints.h"
@@ -165,8 +166,8 @@ static int dpm_read_reg(struct arm_dpm *dpm, struct reg *r, unsigned regnum)
                                        /* core-specific ... ? */
                                        LOG_WARNING("Jazelle PC adjustment unknown");
                                        break;
-                               case ARM_STATE_AARCH64:
-                                       LOG_ERROR("AARCH64: 32bit read requested");
+                               default:
+                                       LOG_WARNING("unknow core state");
                                        break;
                        }
                        break;
@@ -436,20 +437,20 @@ int arm_dpm_write_dirty_registers(struct arm_dpm *dpm, bool bpwp)
 
                                /* cope with special cases */
                                switch (regnum) {
-                                       case 8 ... 12:
-                                               /* r8..r12 "anything but FIQ" case;
-                                                * we "know" core mode is accurate
-                                                * since we haven't changed it yet
-                                                */
-                                               if (arm->core_mode == ARM_MODE_FIQ
-                                                       && ARM_MODE_ANY
-                                                       != mode)
-                                                       tmode = ARM_MODE_USR;
-                                               break;
-                                       case 16:
-                                               /* SPSR */
-                                               regnum++;
-                                               break;
+                               case 8 ... 12:
+                                       /* r8..r12 "anything but FIQ" case;
+                                        * we "know" core mode is accurate
+                                        * since we haven't changed it yet
+                                        */
+                                       if (arm->core_mode == ARM_MODE_FIQ
+                                           && ARM_MODE_ANY
+                                           != mode)
+                                               tmode = ARM_MODE_USR;
+                                       break;
+                               case 16:
+                                       /* SPSR */
+                                       regnum++;
+                                       break;
                                }
 
                                /* REVISIT error checks */
@@ -463,8 +464,8 @@ int arm_dpm_write_dirty_registers(struct arm_dpm *dpm, bool bpwp)
                                continue;
 
                        retval = dpm_write_reg(dpm,
-                                       &cache->reg_list[i],
-                                       regnum);
+                                              &cache->reg_list[i],
+                                              regnum);
                        if (retval != ERROR_OK)
                                goto done;
                }
@@ -929,20 +930,16 @@ void arm_dpm_report_dscr(struct arm_dpm *dpm, uint32_t dscr)
 
        /* Examine debug reason */
        switch (DSCR_ENTRY(dscr)) {
-               case 6: /* Data abort (v6 only) */
-               case 7: /* Prefetch abort (v6 only) */
-               /* FALL THROUGH -- assume a v6 core in abort mode */
-               case 0: /* HALT request from debugger */
-               case 4: /* EDBGRQ */
+               case DSCR_ENTRY_HALT_REQ:       /* HALT request from debugger */
+               case DSCR_ENTRY_EXT_DBG_REQ:    /* EDBGRQ */
                        target->debug_reason = DBG_REASON_DBGRQ;
                        break;
-               case 1: /* HW breakpoint */
-               case 3: /* SW BKPT */
-               case 5: /* vector catch */
+               case DSCR_ENTRY_BREAKPOINT:     /* HW breakpoint */
+               case DSCR_ENTRY_BKPT_INSTR:     /* vector catch */
                        target->debug_reason = DBG_REASON_BREAKPOINT;
                        break;
-               case 2: /* asynch watchpoint */
-               case 10:/* precise watchpoint */
+               case DSCR_ENTRY_IMPRECISE_WATCHPT:      /* asynch watchpoint */
+               case DSCR_ENTRY_PRECISE_WATCHPT:/* precise watchpoint */
                        target->debug_reason = DBG_REASON_WATCHPOINT;
                        break;
                default:
@@ -967,7 +964,7 @@ int arm_dpm_setup(struct arm_dpm *dpm)
 {
        struct arm *arm = dpm->arm;
        struct target *target = arm->target;
-       struct reg_cache *cache;
+       struct reg_cache *cache = 0;
 
        arm->dpm = dpm;
 
@@ -976,7 +973,6 @@ int arm_dpm_setup(struct arm_dpm *dpm)
        arm->read_core_reg = arm_dpm_read_core_reg;
        arm->write_core_reg = arm_dpm_write_core_reg;
 
-       /* avoid duplicating the register cache */
        if (arm->core_cache == NULL) {
                cache = arm_build_reg_cache(target, arm);
                if (!cache)
@@ -1002,9 +998,8 @@ int arm_dpm_setup(struct arm_dpm *dpm)
        /* FIXME add vector catch support */
 
        dpm->nbp = 1 + ((dpm->didr >> 24) & 0xf);
-       dpm->dbp = calloc(dpm->nbp, sizeof *dpm->dbp);
-
        dpm->nwp = 1 + ((dpm->didr >> 28) & 0xf);
+       dpm->dbp = calloc(dpm->nbp, sizeof *dpm->dbp);
        dpm->dwp = calloc(dpm->nwp, sizeof *dpm->dwp);
 
        if (!dpm->dbp || !dpm->dwp) {