- merged XScale branch back into trunk

[openocd.git] / src / target / arm_disassembler.c

diff --git a/src/target/arm_disassembler.c b/src/target/arm_disassembler.c
index 3a9c1f8741325a03ff3ac69f6cf92b5a097e6834..dd77928252fd41131eac1b197d08f357f52f1b14 100644 (file)
--- a/src/target/arm_disassembler.c
+++ b/src/target/arm_disassembler.c
@@ -17,6 +17,10 @@
  *   Free Software Foundation, Inc.,                                       *
  *   59 Temple Place - Suite 330, Boston, MA  02111-1307, USA.             *
  ***************************************************************************/
+#ifdef HAVE_CONFIG_H
+#include "config.h"
+#endif
+
 #include "arm_disassembler.h"
 
 #include "log.h"
@@ -678,7 +682,7 @@ int evaluate_mul_and_extra_ld_st(u32 opcode, u32 address, arm_instruction_t *ins
                /* Multiply (accumulate) long */
                if ((opcode & 0x0f800000) == 0x00800000)
                {
-                       char* mnemonic;
+                       char* mnemonic = NULL;
                        u8 Rm, Rs, RdHi, RdLow, S;
                        Rm = opcode & 0xf;
                        Rs = (opcode & 0xf00) >> 8;
@@ -831,13 +835,16 @@ int evaluate_misc_instr(u32 opcode, u32 address, arm_instruction_t *instruction)
                
                snprintf(instruction->text, 128, "0x%8.8x\t0x%8.8x\tBLX%s r%i",
                                 address, opcode, COND(opcode), Rm);
+                                
+               instruction->info.b_bl_bx_blx.reg_operand = Rm;
+               instruction->info.b_bl_bx_blx.target_address = -1;
        }
        
        /* Enhanced DSP add/subtracts */
        if ((opcode & 0x0000000f0) == 0x00000050)
        {
                u8 Rm, Rd, Rn;
-               char *mnemonic;
+               char *mnemonic = NULL;
                Rm = opcode & 0xf;
                Rd = (opcode & 0xf000) >> 12;
                Rn = (opcode & 0xf0000) >> 16;
@@ -963,7 +970,7 @@ int evaluate_misc_instr(u32 opcode, u32 address, arm_instruction_t *instruction)
 int evaluate_data_proc(u32 opcode, u32 address, arm_instruction_t *instruction)
 {
        u8 I, op, S, Rn, Rd;
-       char *mnemonic;
+       char *mnemonic = NULL;
        char shifter_operand[32];
        
        I = (opcode & 0x02000000) >> 25;
@@ -1074,6 +1081,18 @@ int evaluate_data_proc(u32 opcode, u32 address, arm_instruction_t *instruction)
                        instruction->info.data_proc.shifter_operand.immediate_shift.shift_imm = shift_imm;
                        instruction->info.data_proc.shifter_operand.immediate_shift.shift = shift;
                
+                       /* LSR encodes a shift by 32 bit as 0x0 */
+                       if ((shift == 0x1) && (shift_imm == 0x0))
+                               shift_imm = 0x20;
+               
+                       /* ASR encodes a shift by 32 bit as 0x0 */
+                       if ((shift == 0x2) && (shift_imm == 0x0))
+                               shift_imm = 0x20;
+
+                       /* ROR by 32 bit is actually a RRX */
+                       if ((shift == 0x3) && (shift_imm == 0x0))
+                               shift = 0x4;
+                       
                        if ((shift_imm == 0x0) && (shift == 0x0))
                        {
                                snprintf(shifter_operand, 32, "r%i", Rm);
@@ -1086,22 +1105,19 @@ int evaluate_data_proc(u32 opcode, u32 address, arm_instruction_t *instruction)
                                }
                                else if (shift == 0x1) /* LSR */
                                {
-                                       if (shift_imm == 0x0)
-                                               shift_imm = 0x32;
                                        snprintf(shifter_operand, 32, "r%i, LSR #0x%x", Rm, shift_imm);
                                }
                                else if (shift == 0x2) /* ASR */
                                {
-                                       if (shift_imm == 0x0)
-                                               shift_imm = 0x32;
                                        snprintf(shifter_operand, 32, "r%i, ASR #0x%x", Rm, shift_imm);
                                }
-                               else if (shift == 0x3) /* ROR or RRX */
+                               else if (shift == 0x3) /* ROR */
+                               {
+                                       snprintf(shifter_operand, 32, "r%i, ROR #0x%x", Rm, shift_imm);
+                               }
+                               else if (shift == 0x4) /* RRX */
                                {
-                                       if (shift_imm == 0x0) /* RRX */
-                                               snprintf(shifter_operand, 32, "r%i, RRX", Rm);
-                                       else
-                                               snprintf(shifter_operand, 32, "r%i, ROR #0x%x", Rm, shift_imm);
+                                       snprintf(shifter_operand, 32, "r%i, RRX", Rm);
                                }
                        }
                }
@@ -1126,7 +1142,7 @@ int evaluate_data_proc(u32 opcode, u32 address, arm_instruction_t *instruction)
                        {
                                snprintf(shifter_operand, 32, "r%i, ASR r%i", Rm, Rs);
                        }
-                       else if (shift == 0x3) /* ROR or RRX */
+                       else if (shift == 0x3) /* ROR */
                        {
                                snprintf(shifter_operand, 32, "r%i, ROR r%i", Rm, Rs);
                        }
@@ -1155,7 +1171,7 @@ int evaluate_data_proc(u32 opcode, u32 address, arm_instruction_t *instruction)
        return ERROR_OK;
 }
                
-int evaluate_opcode(u32 opcode, u32 address, arm_instruction_t *instruction)
+int arm_evaluate_opcode(u32 opcode, u32 address, arm_instruction_t *instruction)
 {
        /* clear fields, to avoid confusion */
        memset(instruction, 0, sizeof(arm_instruction_t));
@@ -1243,7 +1259,7 @@ int evaluate_opcode(u32 opcode, u32 address, arm_instruction_t *instruction)
        }
        
        /* catch opcodes with [27:25] = b011 */
-       if ((opcode & 0x0e000000) == 0x04000000)
+       if ((opcode & 0x0e000000) == 0x06000000)
        {
                /* Undefined instruction */
                if ((opcode & 0x00000010) == 0x00000010)
@@ -1298,3 +1314,4 @@ int evaluate_opcode(u32 opcode, u32 address, arm_instruction_t *instruction)
        ERROR("should never reach this point");
        return -1;
 }
+