#define IDR_JEP106_ARM 0x04760000
+#define DP_SELECT_APSEL 0xFF000000
+#define DP_SELECT_APBANK 0x000000F0
+#define DP_SELECT_DPBANK 0x0000000F
+#define DP_SELECT_INVALID 0x00FFFF00 /* Reserved bits one */
+
/**
* This represents an ARM Debug Interface (v5) Access Port (AP).
* Most common is a MEM-AP, for memory access.
uint32_t apsel;
/**
- * Cache for DP_SELECT bits identifying the current AP. A DAP may
- * connect to multiple APs, such as one MEM-AP for general access,
- * another reserved for accessing debug modules, and a JTAG-DP.
- * "-1" indicates no cached value.
- */
- uint32_t ap_current;
-
- /**
- * Cache for DP_SELECT bits identifying the current four-word AP
- * register bank. This caches AP register addresss bits 7:4; JTAG
- * and SWD access primitves pass address bits 3:2; bits 1:0 are zero.
- * "-1" indicates no cached value.
+ * Cache for DP_SELECT register. A value of DP_SELECT_INVALID
+ * indicates no cached value and forces rewrite of the register.
*/
- uint32_t ap_bank_value;
-
- /**
- * Cache for DP_SELECT bits identifying the current four-word DP
- * register bank. This caches DP register addresss bits 7:4; JTAG
- * and SWD access primitves pass address bits 3:2; bits 1:0 are zero.
- */
- uint32_t dp_bank_value;
+ uint32_t select;
/* information about current pending SWjDP-AHBAP transaction */
uint8_t ack;
uint32_t data);
/** AP register read. */
- int (*queue_ap_read)(struct adiv5_dap *dap, unsigned reg,
+ int (*queue_ap_read)(struct adiv5_ap *ap, unsigned reg,
uint32_t *data);
/** AP register write. */
- int (*queue_ap_write)(struct adiv5_dap *dap, unsigned reg,
+ int (*queue_ap_write)(struct adiv5_ap *ap, unsigned reg,
uint32_t data);
/** AP operation abort. */
/**
* Queue an AP register read.
*
- * @param dap The DAP used for reading.
+ * @param ap The AP used for reading.
* @param reg The number of the AP register being read.
* @param data Pointer saying where to store the register's value
* (in host endianness).
*
* @return ERROR_OK for success, else a fault code.
*/
-static inline int dap_queue_ap_read(struct adiv5_dap *dap,
+static inline int dap_queue_ap_read(struct adiv5_ap *ap,
unsigned reg, uint32_t *data)
{
- assert(dap->ops != NULL);
- return dap->ops->queue_ap_read(dap, reg, data);
+ assert(ap->dap->ops != NULL);
+ return ap->dap->ops->queue_ap_read(ap, reg, data);
}
/**
* Queue an AP register write.
*
- * @param dap The DAP used for writing.
+ * @param ap The AP used for writing.
* @param reg The number of the AP register being written.
* @param data Value being written (host endianness)
*
* @return ERROR_OK for success, else a fault code.
*/
-static inline int dap_queue_ap_write(struct adiv5_dap *dap,
+static inline int dap_queue_ap_write(struct adiv5_ap *ap,
unsigned reg, uint32_t data)
{
- assert(dap->ops != NULL);
- return dap->ops->queue_ap_write(dap, reg, data);
+ assert(ap->dap->ops != NULL);
+ return ap->dap->ops->queue_ap_write(ap, reg, data);
}
/**
}
}
-/** Accessor for currently selected DAP-AP number (0..255) */
-static inline uint8_t dap_ap_get_select(struct adiv5_dap *swjdp)
-{
- return (uint8_t)(swjdp->ap_current >> 24);
-}
-
-/* AP selection applies to future AP transactions */
-void dap_ap_select(struct adiv5_dap *dap, uint8_t ap);
-
-/* Queued AP transactions */
-int dap_setup_accessport(struct adiv5_dap *swjdp,
- uint32_t csw, uint32_t tar);
-
-/* Queued MEM-AP memory mapped single word transfers with selection of ap */
-int mem_ap_sel_read_u32(struct adiv5_ap *ap,
+/* Queued MEM-AP memory mapped single word transfers. */
+int mem_ap_read_u32(struct adiv5_ap *ap,
uint32_t address, uint32_t *value);
-int mem_ap_sel_write_u32(struct adiv5_ap *ap,
+int mem_ap_write_u32(struct adiv5_ap *ap,
uint32_t address, uint32_t value);
-/* Synchronous MEM-AP memory mapped single word transfers with selection of ap */
-int mem_ap_sel_read_atomic_u32(struct adiv5_ap *ap,
+/* Synchronous MEM-AP memory mapped single word transfers. */
+int mem_ap_read_atomic_u32(struct adiv5_ap *ap,
uint32_t address, uint32_t *value);
-int mem_ap_sel_write_atomic_u32(struct adiv5_ap *ap,
+int mem_ap_write_atomic_u32(struct adiv5_ap *ap,
uint32_t address, uint32_t value);
-/* Synchronous MEM-AP memory mapped bus block transfers with selection of ap */
-int mem_ap_sel_read_buf(struct adiv5_ap *ap,
+/* Synchronous MEM-AP memory mapped bus block transfers. */
+int mem_ap_read_buf(struct adiv5_ap *ap,
uint8_t *buffer, uint32_t size, uint32_t count, uint32_t address);
-int mem_ap_sel_write_buf(struct adiv5_ap *ap,
+int mem_ap_write_buf(struct adiv5_ap *ap,
const uint8_t *buffer, uint32_t size, uint32_t count, uint32_t address);
-/* Synchronous, non-incrementing buffer functions for accessing fifos, with
- * selection of ap */
-int mem_ap_sel_read_buf_noincr(struct adiv5_ap *ap,
+/* Synchronous, non-incrementing buffer functions for accessing fifos. */
+int mem_ap_read_buf_noincr(struct adiv5_ap *ap,
uint8_t *buffer, uint32_t size, uint32_t count, uint32_t address);
-int mem_ap_sel_write_buf_noincr(struct adiv5_ap *ap,
+int mem_ap_write_buf_noincr(struct adiv5_ap *ap,
const uint8_t *buffer, uint32_t size, uint32_t count, uint32_t address);
/* Create DAP struct */
enum ap_type type_to_find,
struct adiv5_ap **ap_out);
+static inline struct adiv5_ap *dap_ap(struct adiv5_dap *dap, uint8_t ap_num)
+{
+ return &dap->ap[ap_num];
+}
+
/* Lookup CoreSight component */
int dap_lookup_cs_component(struct adiv5_ap *ap,
uint32_t dbgbase, uint8_t type, uint32_t *addr, int32_t *idx);