ARM ADIv5: fix diagnostics for block writes

[openocd.git] / src / target / arm_adi_v5.h

diff --git a/src/target/arm_adi_v5.h b/src/target/arm_adi_v5.h
index bfa5105e986540228d86991dcbd4478f8dd16f48..a807027337f3b6fad436d14333d98cfb1e80a8c8 100644 (file)
--- a/src/target/arm_adi_v5.h
+++ b/src/target/arm_adi_v5.h
@@ -32,25 +32,52 @@
 
 #include "arm_jtag.h"
 
-#define DAP_IR_DPACC   0xA
-#define DAP_IR_APACC   0xB
+/* JTAG instructions/registers for JTAG-DP and SWJ-DP */
+#define JTAG_DP_ABORT          0x8
+#define JTAG_DP_DPACC          0xA
+#define JTAG_DP_APACC          0xB
+#define JTAG_DP_IDCODE         0xE
+
+/* three-bit ACK values for DPACC and APACC reads */
+#define JTAG_ACK_OK_FAULT      0x2
+#define JTAG_ACK_WAIT          0x1
+
+/* three-bit ACK values for SWD access (sent LSB first) */
+#define SWD_ACK_OK             0x4
+#define SWD_ACK_WAIT           0x2
+#define SWD_ACK_FAULT          0x1
 
 #define DPAP_WRITE             0
 #define DPAP_READ              1
 
-/* A[3:0] for DP registers (for JTAG, stored in DPACC) */
-#define DP_ZERO                        0
-#define DP_CTRL_STAT   0x4
-#define DP_SELECT              0x8
-#define DP_RDBUFF              0xC
+/* A[3:0] for DP registers; A[1:0] are always zero.
+ * - JTAG accesses all of these via JTAG_DP_DPACC, except for
+ *   IDCODE (JTAG_DP_IDCODE) and ABORT (JTAG_DP_ABORT).
+ * - SWD accesses these directly, sometimes needing SELECT.CTRLSEL
+ */
+#define DP_IDCODE              0               /* SWD: read */
+#define DP_ABORT               0               /* SWD: write */
+#define DP_CTRL_STAT           0x4             /* r/w */
+#define DP_WCR                 0x4             /* SWD: r/w (mux CTRLSEL) */
+#define DP_RESEND              0x8             /* SWD: read */
+#define DP_SELECT              0x8             /* JTAG: r/w; SWD: write */
+#define DP_RDBUFF              0xC             /* read-only */
+
+/* Fields of the DP's AP ABORT register */
+#define DAPABORT               (1 << 0)
+#define STKCMPCLR              (1 << 1)        /* SWD-only */
+#define STKERRCLR              (1 << 2)        /* SWD-only */
+#define WDERRCLR               (1 << 3)        /* SWD-only */
+#define ORUNERRCLR             (1 << 4)        /* SWD-only */
 
 /* Fields of the DP's CTRL/STAT register */
 #define CORUNDETECT            (1 << 0)
 #define SSTICKYORUN            (1 << 1)
 /* 3:2 - transaction mode (e.g. pushed compare) */
+#define SSTICKYCMP             (1 << 4)
 #define SSTICKYERR             (1 << 5)
-#define READOK                 (1 << 6)
-#define WDATAERR               (1 << 7)
+#define READOK                 (1 << 6)        /* SWD-only */
+#define WDATAERR               (1 << 7)        /* SWD-only */
 /* 11:8 - mask lanes for pushed compare or verify ops */
 /* 21:12 - transaction counter */
 #define CDBGRSTREQ             (1 << 26)
@@ -143,8 +170,8 @@ int dap_ap_write_reg_u32(struct swjdp_common *swjdp,
 int dap_ap_read_reg_u32(struct swjdp_common *swjdp,
                uint32_t addr, uint32_t *value);
 
-/* Queued transactions must be completed with swjdp_transaction_endcheck() */
-int swjdp_transaction_endcheck(struct swjdp_common *swjdp);
+/* Queued JTAG ops must be completed with jtagdp_transaction_endcheck() */
+int jtagdp_transaction_endcheck(struct swjdp_common *swjdp);
 
 /* MEM-AP memory mapped bus single uint32_t register transfers, without endcheck */
 int mem_ap_read_u32(struct swjdp_common *swjdp, uint32_t address, uint32_t *value);