* resources accessed through a MEM-AP.
*/
+#include <helper/list.h>
#include "arm_jtag.h"
-/* FIXME remove these JTAG-specific decls when mem_ap_read_buf_u32()
- * is no longer JTAG-specific
- */
-#define JTAG_DP_DPACC 0xA
-#define JTAG_DP_APACC 0xB
-
/* three-bit ACK values for SWD access (sent LSB first) */
#define SWD_ACK_OK 0x1
#define SWD_ACK_WAIT 0x2
#define IDR_JEP106_ARM 0x04760000
+#define DP_SELECT_APSEL 0xFF000000
+#define DP_SELECT_APBANK 0x000000F0
+#define DP_SELECT_DPBANK 0x0000000F
+#define DP_SELECT_INVALID 0x00FFFF00 /* Reserved bits one */
+
/**
* This represents an ARM Debug Interface (v5) Access Port (AP).
* Most common is a MEM-AP, for memory access.
struct adiv5_dap {
const struct dap_ops *ops;
+ /* dap transaction list for WAIT support */
+ struct list_head cmd_journal;
+
struct jtag_tap *tap;
/* Control config */
uint32_t dp_ctrl_stat;
uint32_t apsel;
/**
- * Cache for DP_SELECT bits identifying the current AP. A DAP may
- * connect to multiple APs, such as one MEM-AP for general access,
- * another reserved for accessing debug modules, and a JTAG-DP.
- * "-1" indicates no cached value.
+ * Cache for DP_SELECT register. A value of DP_SELECT_INVALID
+ * indicates no cached value and forces rewrite of the register.
*/
- uint32_t ap_current;
-
- /**
- * Cache for DP_SELECT bits identifying the current four-word AP
- * register bank. This caches AP register addresss bits 7:4; JTAG
- * and SWD access primitves pass address bits 3:2; bits 1:0 are zero.
- * "-1" indicates no cached value.
- */
- uint32_t ap_bank_value;
-
- /**
- * Cache for DP_SELECT bits identifying the current four-word DP
- * register bank. This caches DP register addresss bits 7:4; JTAG
- * and SWD access primitves pass address bits 3:2; bits 1:0 are zero.
- */
- uint32_t dp_bank_value;
+ uint32_t select;
/* information about current pending SWjDP-AHBAP transaction */
uint8_t ack;
uint32_t data);
/** AP register read. */
- int (*queue_ap_read)(struct adiv5_dap *dap, unsigned reg,
+ int (*queue_ap_read)(struct adiv5_ap *ap, unsigned reg,
uint32_t *data);
/** AP register write. */
- int (*queue_ap_write)(struct adiv5_dap *dap, unsigned reg,
+ int (*queue_ap_write)(struct adiv5_ap *ap, unsigned reg,
uint32_t data);
/** AP operation abort. */
/** Executes all queued DAP operations. */
int (*run)(struct adiv5_dap *dap);
+
+ /** Executes all queued DAP operations but doesn't check
+ * sticky error conditions */
+ int (*sync)(struct adiv5_dap *dap);
};
/*
AP_TYPE_AXI_AP = 0x4, /* AXI Memory-AP */
};
-/* AP selection applies to future AP transactions */
-void dap_ap_select(struct adiv5_dap *dap, uint8_t ap);
-
/**
* Queue a DP register read.
* Note that not all DP registers are readable; also, that JTAG and SWD
unsigned reg, uint32_t *data)
{
assert(ap->dap->ops != NULL);
- dap_ap_select(ap->dap, ap->ap_num);
- return ap->dap->ops->queue_ap_read(ap->dap, reg, data);
+ return ap->dap->ops->queue_ap_read(ap, reg, data);
}
/**
unsigned reg, uint32_t data)
{
assert(ap->dap->ops != NULL);
- dap_ap_select(ap->dap, ap->ap_num);
- return ap->dap->ops->queue_ap_write(ap->dap, reg, data);
+ return ap->dap->ops->queue_ap_write(ap, reg, data);
}
/**
return dap->ops->run(dap);
}
+static inline int dap_sync(struct adiv5_dap *dap)
+{
+ assert(dap->ops != NULL);
+ if (dap->ops->sync)
+ return dap->ops->sync(dap);
+ return ERROR_OK;
+}
+
static inline int dap_dp_read_atomic(struct adiv5_dap *dap, unsigned reg,
uint32_t *value)
{
}
}
-/** Accessor for currently selected DAP-AP number (0..255) */
-static inline uint8_t dap_ap_get_select(struct adiv5_dap *swjdp)
-{
- return (uint8_t)(swjdp->ap_current >> 24);
-}
-
/* Queued MEM-AP memory mapped single word transfers. */
int mem_ap_read_u32(struct adiv5_ap *ap,
uint32_t address, uint32_t *value);