#define WCR_TO_PRESCALE(wcr) ((uint32_t)(7 & ((wcr)))) /* impl defined */
/* Fields of the DP's AP ABORT register */
-#define DAPABORT (1 << 0)
-#define STKCMPCLR (1 << 1) /* SWD-only */
-#define STKERRCLR (1 << 2) /* SWD-only */
-#define WDERRCLR (1 << 3) /* SWD-only */
-#define ORUNERRCLR (1 << 4) /* SWD-only */
+#define DAPABORT (1UL << 0)
+#define STKCMPCLR (1UL << 1) /* SWD-only */
+#define STKERRCLR (1UL << 2) /* SWD-only */
+#define WDERRCLR (1UL << 3) /* SWD-only */
+#define ORUNERRCLR (1UL << 4) /* SWD-only */
/* Fields of the DP's CTRL/STAT register */
-#define CORUNDETECT (1 << 0)
-#define SSTICKYORUN (1 << 1)
+#define CORUNDETECT (1UL << 0)
+#define SSTICKYORUN (1UL << 1)
/* 3:2 - transaction mode (e.g. pushed compare) */
-#define SSTICKYCMP (1 << 4)
-#define SSTICKYERR (1 << 5)
-#define READOK (1 << 6) /* SWD-only */
-#define WDATAERR (1 << 7) /* SWD-only */
+#define SSTICKYCMP (1UL << 4)
+#define SSTICKYERR (1UL << 5)
+#define READOK (1UL << 6) /* SWD-only */
+#define WDATAERR (1UL << 7) /* SWD-only */
/* 11:8 - mask lanes for pushed compare or verify ops */
/* 21:12 - transaction counter */
-#define CDBGRSTREQ (1 << 26)
-#define CDBGRSTACK (1 << 27)
-#define CDBGPWRUPREQ (1 << 28)
-#define CDBGPWRUPACK (1 << 29)
-#define CSYSPWRUPREQ (1 << 30)
-#define CSYSPWRUPACK (1 << 31)
+#define CDBGRSTREQ (1UL << 26)
+#define CDBGRSTACK (1UL << 27)
+#define CDBGPWRUPREQ (1UL << 28)
+#define CDBGPWRUPACK (1UL << 29)
+#define CSYSPWRUPREQ (1UL << 30)
+#define CSYSPWRUPACK (1UL << 31)
/* MEM-AP register addresses */
-/* TODO: rename as MEM_AP_REG_* */
-#define AP_REG_CSW 0x00
-#define AP_REG_TAR 0x04
-#define AP_REG_DRW 0x0C
-#define AP_REG_BD0 0x10
-#define AP_REG_BD1 0x14
-#define AP_REG_BD2 0x18
-#define AP_REG_BD3 0x1C
-#define AP_REG_CFG 0xF4 /* big endian? */
-#define AP_REG_BASE 0xF8
-
+#define MEM_AP_REG_CSW 0x00
+#define MEM_AP_REG_TAR 0x04
+#define MEM_AP_REG_TAR64 0x08 /* RW: Large Physical Address Extension */
+#define MEM_AP_REG_DRW 0x0C /* RW: Data Read/Write register */
+#define MEM_AP_REG_BD0 0x10 /* RW: Banked Data register 0-3 */
+#define MEM_AP_REG_BD1 0x14
+#define MEM_AP_REG_BD2 0x18
+#define MEM_AP_REG_BD3 0x1C
+#define MEM_AP_REG_MBT 0x20 /* --: Memory Barrier Transfer register */
+#define MEM_AP_REG_BASE64 0xF0 /* RO: Debug Base Address (LA) register */
+#define MEM_AP_REG_CFG 0xF4 /* RO: Configuration register */
+#define MEM_AP_REG_BASE 0xF8 /* RO: Debug Base Address register */
/* Generic AP register address */
-#define AP_REG_IDR 0xFC
+#define AP_REG_IDR 0xFC /* RO: Identification Register */
/* Fields of the MEM-AP's CSW register */
#define CSW_8BIT 0
#define CSW_16BIT 1
#define CSW_32BIT 2
-#define CSW_ADDRINC_MASK (3 << 4)
-#define CSW_ADDRINC_OFF 0
-#define CSW_ADDRINC_SINGLE (1 << 4)
-#define CSW_ADDRINC_PACKED (2 << 4)
-#define CSW_DEVICE_EN (1 << 6)
-#define CSW_TRIN_PROG (1 << 7)
-#define CSW_SPIDEN (1 << 23)
+#define CSW_ADDRINC_MASK (3UL << 4)
+#define CSW_ADDRINC_OFF 0UL
+#define CSW_ADDRINC_SINGLE (1UL << 4)
+#define CSW_ADDRINC_PACKED (2UL << 4)
+#define CSW_DEVICE_EN (1UL << 6)
+#define CSW_TRIN_PROG (1UL << 7)
+#define CSW_SPIDEN (1UL << 23)
/* 30:24 - implementation-defined! */
-#define CSW_HPROT (1 << 25) /* ? */
-#define CSW_MASTER_DEBUG (1 << 29) /* ? */
-#define CSW_SPROT (1 << 30)
-#define CSW_DBGSWENABLE (1 << 31)
+#define CSW_HPROT (1UL << 25) /* ? */
+#define CSW_MASTER_DEBUG (1UL << 29) /* ? */
+#define CSW_SPROT (1UL << 30)
+#define CSW_DBGSWENABLE (1UL << 31)
+
+/**
+ * This represents an ARM Debug Interface (v5) Access Port (AP).
+ * Most common is a MEM-AP, for memory access.
+ */
+struct adiv5_ap {
+ /**
+ * DAP this AP belongs to.
+ */
+ struct adiv5_dap *dap;
+
+ /**
+ * Number of this AP.
+ */
+ uint8_t ap_num;
+
+ /**
+ * Default value for (MEM-AP) AP_REG_CSW register.
+ */
+ uint32_t csw_default;
+
+ /**
+ * Cache for (MEM-AP) AP_REG_CSW register value. This is written to
+ * configure an access mode, such as autoincrementing AP_REG_TAR during
+ * word access. "-1" indicates no cached value.
+ */
+ uint32_t csw_value;
+
+ /**
+ * Cache for (MEM-AP) AP_REG_TAR register value This is written to
+ * configure the address being read or written
+ * "-1" indicates no cached value.
+ */
+ uint32_t tar_value;
+
+ /**
+ * Configures how many extra tck clocks are added after starting a
+ * MEM-AP access before we try to read its status (and/or result).
+ */
+ uint32_t memaccess_tck;
+
+ /* Size of TAR autoincrement block, ARM ADI Specification requires at least 10 bits */
+ uint32_t tar_autoincr_block;
+
+ /* true if packed transfers are supported by the MEM-AP */
+ bool packed_transfers;
+
+ /* true if unaligned memory access is not supported by the MEM-AP */
+ bool unaligned_access_bad;
+};
+
/**
* This represents an ARM Debug Interface (v5) Debug Access Port (DAP).
* A DAP has two types of component: one Debug Port (DP), which is a
* transport agent; and at least one Access Port (AP), controlling
- * resource access. Most common is a MEM-AP, for memory access.
+ * resource access.
*
* There are two basic DP transports: JTAG, and ARM's low pin-count SWD.
* Accordingly, this interface is responsible for hiding the transport
struct adiv5_dap {
const struct dap_ops *ops;
- struct arm_jtag *jtag_info;
+ struct jtag_tap *tap;
/* Control config */
uint32_t dp_ctrl_stat;
- uint32_t apcsw[256];
+ struct adiv5_ap ap[256];
+
+ /* The current manually selected AP by the "dap apsel" command */
uint32_t apsel;
/**
*/
uint32_t dp_bank_value;
- /**
- * Cache for (MEM-AP) AP_REG_CSW register value. This is written to
- * configure an access mode, such as autoincrementing AP_REG_TAR during
- * word access. "-1" indicates no cached value.
- */
- uint32_t ap_csw_value;
-
- /**
- * Cache for (MEM-AP) AP_REG_TAR register value This is written to
- * configure the address being read or written
- * "-1" indicates no cached value.
- */
- uint32_t ap_tar_value;
-
/* information about current pending SWjDP-AHBAP transaction */
uint8_t ack;
*/
uint32_t *last_read;
- /**
- * Configures how many extra tck clocks are added after starting a
- * MEM-AP access before we try to read its status (and/or result).
- */
- uint32_t memaccess_tck;
-
- /* Size of TAR autoincrement block, ARM ADI Specification requires at least 10 bits */
- uint32_t tar_autoincr_block;
-
- /* true if packed transfers are supported by the MEM-AP */
- bool packed_transfers;
-
- /* true if unaligned memory access is not supported by the MEM-AP */
- bool unaligned_access_bad;
-
/* The TI TMS470 and TMS570 series processors use a BE-32 memory ordering
* despite lack of support in the ARMv7 architecture. Memory access through
* the AHB-AP has strange byte ordering these processors, and we need to
* swizzle appropriately. */
bool ti_be_32_quirks;
+
+ /**
+ * Signals that an attempt to reestablish communication afresh
+ * should be performed before the next access.
+ */
+ bool do_reconnect;
};
/**
* available until run().
*/
struct dap_ops {
- /** If the DAP transport isn't SWD, it must be JTAG. Upper level
- * code may need to care about the difference in some cases.
- */
- bool is_swd;
-
/** DP register read. */
int (*queue_dp_read)(struct adiv5_dap *dap, unsigned reg,
uint32_t *data);
int ret;
uint32_t regval;
- LOG_DEBUG("DAP: poll %x, mask 0x08%" PRIx32 ", value 0x%08" PRIx32,
+ LOG_DEBUG("DAP: poll %x, mask 0x%08" PRIx32 ", value 0x%08" PRIx32,
reg, mask, value);
do {
ret = dap_dp_read_atomic(dap, reg, ®val);
if (!timeout) {
LOG_DEBUG("DAP: poll %x timeout", reg);
- return ERROR_FAIL;
+ return ERROR_WAIT;
} else {
return ERROR_OK;
}
int dap_setup_accessport(struct adiv5_dap *swjdp,
uint32_t csw, uint32_t tar);
-/* Queued MEM-AP memory mapped single word transfers */
-int mem_ap_read_u32(struct adiv5_dap *swjdp, uint32_t address, uint32_t *value);
-int mem_ap_write_u32(struct adiv5_dap *swjdp, uint32_t address, uint32_t value);
-
-/* Synchronous MEM-AP memory mapped single word transfers */
-int mem_ap_read_atomic_u32(struct adiv5_dap *swjdp,
- uint32_t address, uint32_t *value);
-int mem_ap_write_atomic_u32(struct adiv5_dap *swjdp,
- uint32_t address, uint32_t value);
-
/* Queued MEM-AP memory mapped single word transfers with selection of ap */
int mem_ap_sel_read_u32(struct adiv5_dap *swjdp, uint8_t ap,
uint32_t address, uint32_t *value);
int mem_ap_sel_write_atomic_u32(struct adiv5_dap *swjdp, uint8_t ap,
uint32_t address, uint32_t value);
-/* Synchronous MEM-AP memory mapped bus block transfers */
-int mem_ap_read(struct adiv5_dap *dap, uint8_t *buffer, uint32_t size,
- uint32_t count, uint32_t address, bool addrinc);
-int mem_ap_write(struct adiv5_dap *dap, const uint8_t *buffer, uint32_t size,
- uint32_t count, uint32_t address, bool addrinc);
-
/* Synchronous MEM-AP memory mapped bus block transfers with selection of ap */
int mem_ap_sel_read_buf(struct adiv5_dap *swjdp, uint8_t ap,
uint8_t *buffer, uint32_t size, uint32_t count, uint32_t address);
int mem_ap_sel_write_buf_noincr(struct adiv5_dap *swjdp, uint8_t ap,
const uint8_t *buffer, uint32_t size, uint32_t count, uint32_t address);
+/* Create DAP struct */
+struct adiv5_dap *dap_init(void);
+
/* Initialisation of the debug system, power domains and registers */
-int ahbap_debugport_init(struct adiv5_dap *swjdp);
+int ahbap_debugport_init(struct adiv5_dap *swjdp, uint8_t apsel);
/* Probe the AP for ROM Table location */
int dap_get_debugbase(struct adiv5_dap *dap, int ap,
/* Lookup CoreSight component */
int dap_lookup_cs_component(struct adiv5_dap *dap, int ap,
- uint32_t dbgbase, uint8_t type, uint32_t *addr);
+ uint32_t dbgbase, uint8_t type, uint32_t *addr, int32_t *idx);
struct target;
Code Review / openocd.git / blobdiff