+#define BANK_REG(bank, reg) (((bank) << 4) | (reg))
+
+/* A[3:0] for DP registers; A[1:0] are always zero.
+ * - JTAG accesses all of these via JTAG_DP_DPACC, except for
+ * IDCODE (JTAG_DP_IDCODE) and ABORT (JTAG_DP_ABORT).
+ * - SWD accesses these directly, sometimes needing SELECT.DPBANKSEL
+ */
+#define DP_DPIDR BANK_REG(0x0, 0x0) /* DPv1+: ro */
+#define DP_ABORT BANK_REG(0x0, 0x0) /* DPv1+: SWD: wo */
+#define DP_CTRL_STAT BANK_REG(0x0, 0x4) /* DPv0+: rw */
+#define DP_DLCR BANK_REG(0x1, 0x4) /* DPv1+: SWD: rw */
+#define DP_TARGETID BANK_REG(0x2, 0x4) /* DPv2: ro */
+#define DP_DLPIDR BANK_REG(0x3, 0x4) /* DPv2: ro */
+#define DP_EVENTSTAT BANK_REG(0x4, 0x4) /* DPv2: ro */
+#define DP_RESEND BANK_REG(0x0, 0x8) /* DPv1+: SWD: ro */
+#define DP_SELECT BANK_REG(0x0, 0x8) /* DPv0+: JTAG: rw; SWD: wo */
+#define DP_RDBUFF BANK_REG(0x0, 0xC) /* DPv0+: ro */
+#define DP_TARGETSEL BANK_REG(0x0, 0xC) /* DPv2: SWD: wo */
+
+#define DLCR_TO_TRN(dlcr) ((uint32_t)(1 + ((3 & (dlcr)) >> 8))) /* 1..4 clocks */
+
+/* Fields of the DP's AP ABORT register */
+#define DAPABORT (1UL << 0)
+#define STKCMPCLR (1UL << 1) /* SWD-only */
+#define STKERRCLR (1UL << 2) /* SWD-only */
+#define WDERRCLR (1UL << 3) /* SWD-only */
+#define ORUNERRCLR (1UL << 4) /* SWD-only */
+
+/* Fields of the DP's CTRL/STAT register */
+#define CORUNDETECT (1UL << 0)
+#define SSTICKYORUN (1UL << 1)
+/* 3:2 - transaction mode (e.g. pushed compare) */
+#define SSTICKYCMP (1UL << 4)
+#define SSTICKYERR (1UL << 5)
+#define READOK (1UL << 6) /* SWD-only */
+#define WDATAERR (1UL << 7) /* SWD-only */
+/* 11:8 - mask lanes for pushed compare or verify ops */
+/* 21:12 - transaction counter */
+#define CDBGRSTREQ (1UL << 26)
+#define CDBGRSTACK (1UL << 27)
+#define CDBGPWRUPREQ (1UL << 28)
+#define CDBGPWRUPACK (1UL << 29)
+#define CSYSPWRUPREQ (1UL << 30)
+#define CSYSPWRUPACK (1UL << 31)
+
+/* MEM-AP register addresses */
+#define MEM_AP_REG_CSW 0x00
+#define MEM_AP_REG_TAR 0x04
+#define MEM_AP_REG_TAR64 0x08 /* RW: Large Physical Address Extension */
+#define MEM_AP_REG_DRW 0x0C /* RW: Data Read/Write register */
+#define MEM_AP_REG_BD0 0x10 /* RW: Banked Data register 0-3 */
+#define MEM_AP_REG_BD1 0x14
+#define MEM_AP_REG_BD2 0x18
+#define MEM_AP_REG_BD3 0x1C
+#define MEM_AP_REG_MBT 0x20 /* --: Memory Barrier Transfer register */
+#define MEM_AP_REG_BASE64 0xF0 /* RO: Debug Base Address (LA) register */
+#define MEM_AP_REG_CFG 0xF4 /* RO: Configuration register */
+#define MEM_AP_REG_BASE 0xF8 /* RO: Debug Base Address register */
+/* Generic AP register address */
+#define AP_REG_IDR 0xFC /* RO: Identification Register */
+
+/* Fields of the MEM-AP's CSW register */
+#define CSW_SIZE_MASK 7