if (csw != dap->ap_csw_value) {
/* LOG_DEBUG("DAP: Set CSW %x",csw); */
- int retval = dap_queue_ap_write(dap, AP_REG_CSW, csw);
+ int retval = dap_queue_ap_write(dap, MEM_AP_REG_CSW, csw);
if (retval != ERROR_OK)
return retval;
dap->ap_csw_value = csw;
{
if (tar != dap->ap_tar_value || dap->ap_csw_value & CSW_ADDRINC_MASK) {
/* LOG_DEBUG("DAP: Set TAR %x",tar); */
- int retval = dap_queue_ap_write(dap, AP_REG_TAR, tar);
+ int retval = dap_queue_ap_write(dap, MEM_AP_REG_TAR, tar);
if (retval != ERROR_OK)
return retval;
dap->ap_tar_value = tar;
* Queue transactions setting up transfer parameters for the
* currently selected MEM-AP.
*
- * Subsequent transfers using registers like AP_REG_DRW or AP_REG_BD2
+ * Subsequent transfers using registers like MEM_AP_REG_DRW or MEM_AP_REG_BD2
* initiate data reads or writes using memory or peripheral addresses.
* If the CSW is configured for it, the TAR may be automatically
* incremented after each transfer.
if (retval != ERROR_OK)
return retval;
- return dap_queue_ap_read(dap, AP_REG_BD0 | (address & 0xC), value);
+ return dap_queue_ap_read(dap, MEM_AP_REG_BD0 | (address & 0xC), value);
}
/**
if (retval != ERROR_OK)
return retval;
- return dap_queue_ap_write(dap, AP_REG_BD0 | (address & 0xC),
+ return dap_queue_ap_write(dap, MEM_AP_REG_BD0 | (address & 0xC),
value);
}
nbytes -= this_size;
- retval = dap_queue_ap_write(dap, AP_REG_DRW, outvalue);
+ retval = dap_queue_ap_write(dap, MEM_AP_REG_DRW, outvalue);
if (retval != ERROR_OK)
break;
if (retval != ERROR_OK) {
uint32_t tar;
- if (dap_queue_ap_read(dap, AP_REG_TAR, &tar) == ERROR_OK
+ if (dap_queue_ap_read(dap, MEM_AP_REG_TAR, &tar) == ERROR_OK
&& dap_run(dap) == ERROR_OK)
LOG_ERROR("Failed to write memory at 0x%08"PRIx32, tar);
else
if (retval != ERROR_OK)
break;
- retval = dap_queue_ap_read(dap, AP_REG_DRW, read_ptr++);
+ retval = dap_queue_ap_read(dap, MEM_AP_REG_DRW, read_ptr++);
if (retval != ERROR_OK)
break;
* at least give the caller what we have. */
if (retval != ERROR_OK) {
uint32_t tar;
- if (dap_queue_ap_read(dap, AP_REG_TAR, &tar) == ERROR_OK
+ if (dap_queue_ap_read(dap, MEM_AP_REG_TAR, &tar) == ERROR_OK
&& dap_run(dap) == ERROR_OK) {
LOG_ERROR("Failed to read memory at 0x%08"PRIx32, tar);
if (nbytes > tar - address)
if (retval != ERROR_OK)
continue;
- retval = dap_queue_ap_read(dap, AP_REG_CSW, &csw);
+ retval = dap_queue_ap_read(dap, MEM_AP_REG_CSW, &csw);
if (retval != ERROR_OK)
continue;
- retval = dap_queue_ap_read(dap, AP_REG_CFG, &cfg);
+ retval = dap_queue_ap_read(dap, MEM_AP_REG_CFG, &cfg);
if (retval != ERROR_OK)
continue;
if (ap >= 256)
return ERROR_COMMAND_SYNTAX_ERROR;
- ap_old = dap->ap_current;
+ ap_old = dap_ap_get_select(dap);
dap_ap_select(dap, ap);
- retval = dap_queue_ap_read(dap, AP_REG_BASE, dbgbase);
+ retval = dap_queue_ap_read(dap, MEM_AP_REG_BASE, dbgbase);
if (retval != ERROR_OK)
return retval;
retval = dap_queue_ap_read(dap, AP_REG_IDR, apid);
return ERROR_COMMAND_SYNTAX_ERROR;
*addr = 0;
- ap_old = dap->ap_current;
+ ap_old = dap_ap_get_select(dap);
dap_ap_select(dap, ap);
do {
uint32_t c_cid0, c_cid1, c_cid2, c_cid3;
uint32_t c_pid0, c_pid1, c_pid2, c_pid3, c_pid4;
uint32_t component_base;
- unsigned part_num;
+ uint32_t part_num;
const char *type, *full;
component_base = (dbgbase & 0xFFFFF000) + (romentry & 0xFFFFF000);
if (retval != ERROR_OK)
return retval;
- ap_old = dap->ap_current;
+ ap_old = dap_ap_get_select(dap);
dap_ap_select(dap, ap);
/* Now we read ROM table ID registers, ref. ARM IHI 0029B sec */
* though they're not common for now. This should
* use the ID register to verify it's a MEM-AP.
*/
- retval = dap_queue_ap_read(dap, AP_REG_BASE, &baseaddr);
+ retval = dap_queue_ap_read(dap, MEM_AP_REG_BASE, &baseaddr);
if (retval != ERROR_OK)
return retval;
retval = dap_run(dap);