arm_adi_v5: add dap apreg command for AP register read/write

[openocd.git] / src / target / arm_adi_v5.c

diff --git a/src/target/arm_adi_v5.c b/src/target/arm_adi_v5.c
index d76f48916d2648539e33293fc8d304833cbaee4d..f58afdc0a9f84d8864fbba101154e3586c6cd90d 100644 (file)
--- a/src/target/arm_adi_v5.c
+++ b/src/target/arm_adi_v5.c
@@ -24,9 +24,7 @@
  *   GNU General Public License for more details.                          *
  *                                                                         *
  *   You should have received a copy of the GNU General Public License     *
- *   along with this program; if not, write to the                         *
- *   Free Software Foundation, Inc.,                                       *
- *   51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.           *
+ *   along with this program.  If not, see <http://www.gnu.org/licenses/>. *
  ***************************************************************************/
 
 /**
@@ -1039,7 +1037,11 @@ static const struct {
        { ARM_ID, 0xd03, "Cortex-A53 Debug",           "(Debug Unit)", },
        { ARM_ID, 0xd07, "Cortex-A57 Debug",           "(Debug Unit)", },
        { ARM_ID, 0xd08, "Cortex-A72 Debug",           "(Debug Unit)", },
+       { 0x097,  0x9af, "MSP432 ROM",                 "(ROM Table)" },
        { 0x09f,  0xcd0, "Atmel CPU with DSU",         "(CPU)" },
+       { 0x0c1,  0x1db, "XMC4500 ROM",                "(ROM Table)" },
+       { 0x0c1,  0x1df, "XMC4700/4800 ROM",           "(ROM Table)" },
+       { 0x0c1,  0x1ed, "XMC1000 ROM",                "(ROM Table)" },
        { 0x0E5,  0x000, "SHARC+/Blackfin+",           "", },
        { 0x0F0,  0x440, "Qualcomm QDSS Component v1", "(Qualcomm Designed CoreSight Component v1)", },
        /* legacy comment: 0x113: what? */
@@ -1554,6 +1556,45 @@ COMMAND_HANDLER(dap_apid_command)
        return retval;
 }
 
+COMMAND_HANDLER(dap_apreg_command)
+{
+       struct target *target = get_current_target(CMD_CTX);
+       struct arm *arm = target_to_arm(target);
+       struct adiv5_dap *dap = arm->dap;
+
+       uint32_t apsel, reg, value;
+       int retval;
+
+       if (CMD_ARGC < 2 || CMD_ARGC > 3)
+               return ERROR_COMMAND_SYNTAX_ERROR;
+
+       COMMAND_PARSE_NUMBER(u32, CMD_ARGV[0], apsel);
+       /* AP address is in bits 31:24 of DP_SELECT */
+       if (apsel >= 256)
+               return ERROR_COMMAND_SYNTAX_ERROR;
+
+       COMMAND_PARSE_NUMBER(u32, CMD_ARGV[1], reg);
+       if (reg >= 256 || (reg & 3))
+               return ERROR_COMMAND_SYNTAX_ERROR;
+
+       if (CMD_ARGC == 3) {
+               COMMAND_PARSE_NUMBER(u32, CMD_ARGV[2], value);
+               retval = dap_queue_ap_write(dap_ap(dap, apsel), reg, value);
+       } else {
+               retval = dap_queue_ap_read(dap_ap(dap, apsel), reg, &value);
+       }
+       if (retval == ERROR_OK)
+               retval = dap_run(dap);
+
+       if (retval != ERROR_OK)
+               return retval;
+
+       if (CMD_ARGC == 2)
+               command_print(CMD_CTX, "0x%08" PRIx32, value);
+
+       return retval;
+}
+
 COMMAND_HANDLER(dap_ti_be_32_quirks_command)
 {
        struct target *target = get_current_target(CMD_CTX);
@@ -1613,6 +1654,14 @@ static const struct command_registration dap_commands[] = {
                        "(default currently selected AP)",
                .usage = "[ap_num]",
        },
+       {
+               .name = "apreg",
+               .handler = dap_apreg_command,
+               .mode = COMMAND_EXEC,
+               .help = "read/write a register from AP "
+                       "(reg is byte address of a word register, like 0 4 8...)",
+               .usage = "ap_num reg [value]",
+       },
        {
                .name = "baseaddr",
                .handler = dap_baseaddr_command,