* Values MUST BE UPDATED BEFORE AP ACCESS.
*/
dap->ap_bank_value = -1;
- dap->ap_csw_value = -1;
- dap->ap_tar_value = -1;
}
}
static int dap_setup_accessport_csw(struct adiv5_dap *dap, uint32_t csw)
{
csw = csw | CSW_DBGSWENABLE | CSW_MASTER_DEBUG | CSW_HPROT |
- dap->apcsw[dap->ap_current >> 24];
+ dap->ap[dap_ap_get_select(dap)].csw_default;
- if (csw != dap->ap_csw_value) {
+ if (csw != dap->ap[dap_ap_get_select(dap)].csw_value) {
/* LOG_DEBUG("DAP: Set CSW %x",csw); */
- int retval = dap_queue_ap_write(dap, AP_REG_CSW, csw);
+ int retval = dap_queue_ap_write(dap, MEM_AP_REG_CSW, csw);
if (retval != ERROR_OK)
return retval;
- dap->ap_csw_value = csw;
+ dap->ap[dap_ap_get_select(dap)].csw_value = csw;
}
return ERROR_OK;
}
static int dap_setup_accessport_tar(struct adiv5_dap *dap, uint32_t tar)
{
- if (tar != dap->ap_tar_value || dap->ap_csw_value & CSW_ADDRINC_MASK) {
+ if (tar != dap->ap[dap_ap_get_select(dap)].tar_value ||
+ (dap->ap[dap_ap_get_select(dap)].csw_value & CSW_ADDRINC_MASK)) {
/* LOG_DEBUG("DAP: Set TAR %x",tar); */
- int retval = dap_queue_ap_write(dap, AP_REG_TAR, tar);
+ int retval = dap_queue_ap_write(dap, MEM_AP_REG_TAR, tar);
if (retval != ERROR_OK)
return retval;
- dap->ap_tar_value = tar;
+ dap->ap[dap_ap_get_select(dap)].tar_value = tar;
}
return ERROR_OK;
}
* Queue transactions setting up transfer parameters for the
* currently selected MEM-AP.
*
- * Subsequent transfers using registers like AP_REG_DRW or AP_REG_BD2
+ * Subsequent transfers using registers like MEM_AP_REG_DRW or MEM_AP_REG_BD2
* initiate data reads or writes using memory or peripheral addresses.
* If the CSW is configured for it, the TAR may be automatically
* incremented after each transfer.
*
* @return ERROR_OK for success. Otherwise a fault code.
*/
-int mem_ap_read_u32(struct adiv5_dap *dap, uint32_t address,
+static int mem_ap_read_u32(struct adiv5_dap *dap, uint32_t address,
uint32_t *value)
{
int retval;
if (retval != ERROR_OK)
return retval;
- return dap_queue_ap_read(dap, AP_REG_BD0 | (address & 0xC), value);
+ return dap_queue_ap_read(dap, MEM_AP_REG_BD0 | (address & 0xC), value);
}
/**
* @return ERROR_OK for success; *value holds the result.
* Otherwise a fault code.
*/
-int mem_ap_read_atomic_u32(struct adiv5_dap *dap, uint32_t address,
+static int mem_ap_read_atomic_u32(struct adiv5_dap *dap, uint32_t address,
uint32_t *value)
{
int retval;
*
* @return ERROR_OK for success. Otherwise a fault code.
*/
-int mem_ap_write_u32(struct adiv5_dap *dap, uint32_t address,
+static int mem_ap_write_u32(struct adiv5_dap *dap, uint32_t address,
uint32_t value)
{
int retval;
if (retval != ERROR_OK)
return retval;
- return dap_queue_ap_write(dap, AP_REG_BD0 | (address & 0xC),
+ return dap_queue_ap_write(dap, MEM_AP_REG_BD0 | (address & 0xC),
value);
}
*
* @return ERROR_OK for success; the data was written. Otherwise a fault code.
*/
-int mem_ap_write_atomic_u32(struct adiv5_dap *dap, uint32_t address,
+static int mem_ap_write_atomic_u32(struct adiv5_dap *dap, uint32_t address,
uint32_t value)
{
int retval = mem_ap_write_u32(dap, address, value);
* should normally be true, except when writing to e.g. a FIFO.
* @return ERROR_OK on success, otherwise an error code.
*/
-int mem_ap_write(struct adiv5_dap *dap, const uint8_t *buffer, uint32_t size, uint32_t count,
+static int mem_ap_write(struct adiv5_dap *dap, const uint8_t *buffer, uint32_t size, uint32_t count,
uint32_t address, bool addrinc)
{
+ struct adiv5_ap *ap = &dap->ap[dap_ap_get_select(dap)];
size_t nbytes = size * count;
const uint32_t csw_addrincr = addrinc ? CSW_ADDRINC_SINGLE : CSW_ADDRINC_OFF;
uint32_t csw_size;
return ERROR_TARGET_UNALIGNED_ACCESS;
}
- if (dap->unaligned_access_bad && (address % size != 0))
+ if (ap->unaligned_access_bad && (address % size != 0))
return ERROR_TARGET_UNALIGNED_ACCESS;
retval = dap_setup_accessport_tar(dap, address ^ addr_xor);
uint32_t this_size = size;
/* Select packed transfer if possible */
- if (addrinc && dap->packed_transfers && nbytes >= 4
- && max_tar_block_size(dap->tar_autoincr_block, address) >= 4) {
+ if (addrinc && ap->packed_transfers && nbytes >= 4
+ && max_tar_block_size(ap->tar_autoincr_block, address) >= 4) {
this_size = 4;
retval = dap_setup_accessport_csw(dap, csw_size | CSW_ADDRINC_PACKED);
} else {
nbytes -= this_size;
- retval = dap_queue_ap_write(dap, AP_REG_DRW, outvalue);
+ retval = dap_queue_ap_write(dap, MEM_AP_REG_DRW, outvalue);
if (retval != ERROR_OK)
break;
/* Rewrite TAR if it wrapped or we're xoring addresses */
- if (addrinc && (addr_xor || (address % dap->tar_autoincr_block < size && nbytes > 0))) {
+ if (addrinc && (addr_xor || (address % ap->tar_autoincr_block < size && nbytes > 0))) {
retval = dap_setup_accessport_tar(dap, address ^ addr_xor);
if (retval != ERROR_OK)
break;
if (retval != ERROR_OK) {
uint32_t tar;
- if (dap_queue_ap_read(dap, AP_REG_TAR, &tar) == ERROR_OK
+ if (dap_queue_ap_read(dap, MEM_AP_REG_TAR, &tar) == ERROR_OK
&& dap_run(dap) == ERROR_OK)
LOG_ERROR("Failed to write memory at 0x%08"PRIx32, tar);
else
* should normally be true, except when reading from e.g. a FIFO.
* @return ERROR_OK on success, otherwise an error code.
*/
-int mem_ap_read(struct adiv5_dap *dap, uint8_t *buffer, uint32_t size, uint32_t count,
+static int mem_ap_read(struct adiv5_dap *dap, uint8_t *buffer, uint32_t size, uint32_t count,
uint32_t adr, bool addrinc)
{
+ struct adiv5_ap *ap = &dap->ap[dap_ap_get_select(dap)];
size_t nbytes = size * count;
const uint32_t csw_addrincr = addrinc ? CSW_ADDRINC_SINGLE : CSW_ADDRINC_OFF;
uint32_t csw_size;
else
return ERROR_TARGET_UNALIGNED_ACCESS;
- if (dap->unaligned_access_bad && (adr % size != 0))
+ if (ap->unaligned_access_bad && (adr % size != 0))
return ERROR_TARGET_UNALIGNED_ACCESS;
/* Allocate buffer to hold the sequence of DRW reads that will be made. This is a significant
uint32_t this_size = size;
/* Select packed transfer if possible */
- if (addrinc && dap->packed_transfers && nbytes >= 4
- && max_tar_block_size(dap->tar_autoincr_block, address) >= 4) {
+ if (addrinc && ap->packed_transfers && nbytes >= 4
+ && max_tar_block_size(ap->tar_autoincr_block, address) >= 4) {
this_size = 4;
retval = dap_setup_accessport_csw(dap, csw_size | CSW_ADDRINC_PACKED);
} else {
if (retval != ERROR_OK)
break;
- retval = dap_queue_ap_read(dap, AP_REG_DRW, read_ptr++);
+ retval = dap_queue_ap_read(dap, MEM_AP_REG_DRW, read_ptr++);
if (retval != ERROR_OK)
break;
address += this_size;
/* Rewrite TAR if it wrapped */
- if (addrinc && address % dap->tar_autoincr_block < size && nbytes > 0) {
+ if (addrinc && address % ap->tar_autoincr_block < size && nbytes > 0) {
retval = dap_setup_accessport_tar(dap, address);
if (retval != ERROR_OK)
break;
* at least give the caller what we have. */
if (retval != ERROR_OK) {
uint32_t tar;
- if (dap_queue_ap_read(dap, AP_REG_TAR, &tar) == ERROR_OK
+ if (dap_queue_ap_read(dap, MEM_AP_REG_TAR, &tar) == ERROR_OK
&& dap_run(dap) == ERROR_OK) {
LOG_ERROR("Failed to read memory at 0x%08"PRIx32, tar);
if (nbytes > tar - address)
while (nbytes > 0) {
uint32_t this_size = size;
- if (addrinc && dap->packed_transfers && nbytes >= 4
- && max_tar_block_size(dap->tar_autoincr_block, address) >= 4) {
+ if (addrinc && ap->packed_transfers && nbytes >= 4
+ && max_tar_block_size(ap->tar_autoincr_block, address) >= 4) {
this_size = 4;
}
/*--------------------------------------------------------------------------*/
+/**
+ * Create a new DAP
+ */
+struct adiv5_dap *dap_init(void)
+{
+ struct adiv5_dap *dap = calloc(1, sizeof(struct adiv5_dap));
+ int i;
+ /* Set up with safe defaults */
+ for (i = 0; i <= 255; i++) {
+ /* memaccess_tck max is 255 */
+ dap->ap[i].memaccess_tck = 255;
+ /* Number of bits for tar autoincrement, impl. dep. at least 10 */
+ dap->ap[i].tar_autoincr_block = (1<<10);
+ }
+ return dap;
+}
+
/**
* Initialize a DAP. This sets up the power domains, prepares the DP
* for further use, and arranges to use AP #0 for all AP operations
* in layering. (JTAG is useful without any debug target; but not SWD.)
* And this may not even use an AHB-AP ... e.g. DAP-Lite uses an APB-AP.
*/
-int ahbap_debugport_init(struct adiv5_dap *dap)
+int ahbap_debugport_init(struct adiv5_dap *dap, uint8_t apsel)
{
+ /* check that we support packed transfers */
+ uint32_t csw, cfg;
int retval;
+ struct adiv5_ap *ap = &dap->ap[apsel];
LOG_DEBUG(" ");
* Should we probe, or take a hint from the caller?
* Presumably we can ignore the possibility of multiple APs.
*/
- dap->ap_current = !0;
- dap_ap_select(dap, 0);
+ dap->ap_current = -1;
+ dap_ap_select(dap, apsel);
+ dap->last_read = NULL;
- /* DP initialization */
+ for (size_t i = 0; i < 10; i++) {
+ /* DP initialization */
- retval = dap_queue_dp_read(dap, DP_CTRL_STAT, NULL);
- if (retval != ERROR_OK)
- return retval;
+ dap->dp_bank_value = 0;
- retval = dap_queue_dp_write(dap, DP_CTRL_STAT, SSTICKYERR);
- if (retval != ERROR_OK)
- return retval;
+ retval = dap_queue_dp_read(dap, DP_CTRL_STAT, NULL);
+ if (retval != ERROR_OK)
+ continue;
- retval = dap_queue_dp_read(dap, DP_CTRL_STAT, NULL);
- if (retval != ERROR_OK)
- return retval;
+ retval = dap_queue_dp_write(dap, DP_CTRL_STAT, SSTICKYERR);
+ if (retval != ERROR_OK)
+ continue;
- dap->dp_ctrl_stat = CDBGPWRUPREQ | CSYSPWRUPREQ;
- retval = dap_queue_dp_write(dap, DP_CTRL_STAT, dap->dp_ctrl_stat);
- if (retval != ERROR_OK)
- return retval;
+ retval = dap_queue_dp_read(dap, DP_CTRL_STAT, NULL);
+ if (retval != ERROR_OK)
+ continue;
- /* Check that we have debug power domains activated */
- LOG_DEBUG("DAP: wait CDBGPWRUPACK");
- retval = dap_dp_poll_register(dap, DP_CTRL_STAT,
- CDBGPWRUPACK, CDBGPWRUPACK,
- DAP_POWER_DOMAIN_TIMEOUT);
- if (retval != ERROR_OK)
- return retval;
+ dap->dp_ctrl_stat = CDBGPWRUPREQ | CSYSPWRUPREQ;
+ retval = dap_queue_dp_write(dap, DP_CTRL_STAT, dap->dp_ctrl_stat);
+ if (retval != ERROR_OK)
+ continue;
- LOG_DEBUG("DAP: wait CSYSPWRUPACK");
- retval = dap_dp_poll_register(dap, DP_CTRL_STAT,
- CSYSPWRUPACK, CSYSPWRUPACK,
- DAP_POWER_DOMAIN_TIMEOUT);
- if (retval != ERROR_OK)
- return retval;
+ /* Check that we have debug power domains activated */
+ LOG_DEBUG("DAP: wait CDBGPWRUPACK");
+ retval = dap_dp_poll_register(dap, DP_CTRL_STAT,
+ CDBGPWRUPACK, CDBGPWRUPACK,
+ DAP_POWER_DOMAIN_TIMEOUT);
+ if (retval != ERROR_OK)
+ continue;
- retval = dap_queue_dp_read(dap, DP_CTRL_STAT, NULL);
- if (retval != ERROR_OK)
- return retval;
- /* With debug power on we can activate OVERRUN checking */
- dap->dp_ctrl_stat = CDBGPWRUPREQ | CSYSPWRUPREQ | CORUNDETECT;
- retval = dap_queue_dp_write(dap, DP_CTRL_STAT, dap->dp_ctrl_stat);
- if (retval != ERROR_OK)
- return retval;
- retval = dap_queue_dp_read(dap, DP_CTRL_STAT, NULL);
- if (retval != ERROR_OK)
- return retval;
+ LOG_DEBUG("DAP: wait CSYSPWRUPACK");
+ retval = dap_dp_poll_register(dap, DP_CTRL_STAT,
+ CSYSPWRUPACK, CSYSPWRUPACK,
+ DAP_POWER_DOMAIN_TIMEOUT);
+ if (retval != ERROR_OK)
+ continue;
- /* check that we support packed transfers */
- uint32_t csw, cfg;
+ retval = dap_queue_dp_read(dap, DP_CTRL_STAT, NULL);
+ if (retval != ERROR_OK)
+ continue;
+ /* With debug power on we can activate OVERRUN checking */
+ dap->dp_ctrl_stat = CDBGPWRUPREQ | CSYSPWRUPREQ | CORUNDETECT;
+ retval = dap_queue_dp_write(dap, DP_CTRL_STAT, dap->dp_ctrl_stat);
+ if (retval != ERROR_OK)
+ continue;
+ retval = dap_queue_dp_read(dap, DP_CTRL_STAT, NULL);
+ if (retval != ERROR_OK)
+ continue;
- retval = dap_setup_accessport(dap, CSW_8BIT | CSW_ADDRINC_PACKED, 0);
- if (retval != ERROR_OK)
- return retval;
+ retval = dap_setup_accessport(dap, CSW_8BIT | CSW_ADDRINC_PACKED, 0);
+ if (retval != ERROR_OK)
+ continue;
- retval = dap_queue_ap_read(dap, AP_REG_CSW, &csw);
- if (retval != ERROR_OK)
- return retval;
+ retval = dap_queue_ap_read(dap, MEM_AP_REG_CSW, &csw);
+ if (retval != ERROR_OK)
+ continue;
- retval = dap_queue_ap_read(dap, AP_REG_CFG, &cfg);
- if (retval != ERROR_OK)
- return retval;
+ retval = dap_queue_ap_read(dap, MEM_AP_REG_CFG, &cfg);
+ if (retval != ERROR_OK)
+ continue;
+
+ retval = dap_run(dap);
+ if (retval != ERROR_OK)
+ continue;
+
+ break;
+ }
- retval = dap_run(dap);
if (retval != ERROR_OK)
return retval;
if (csw & CSW_ADDRINC_PACKED)
- dap->packed_transfers = true;
+ ap->packed_transfers = true;
else
- dap->packed_transfers = false;
+ ap->packed_transfers = false;
/* Packed transfers on TI BE-32 processors do not work correctly in
* many cases. */
if (dap->ti_be_32_quirks)
- dap->packed_transfers = false;
+ ap->packed_transfers = false;
LOG_DEBUG("MEM_AP Packed Transfers: %s",
- dap->packed_transfers ? "enabled" : "disabled");
+ ap->packed_transfers ? "enabled" : "disabled");
/* The ARM ADI spec leaves implementation-defined whether unaligned
* memory accesses work, only work partially, or cause a sticky error.
* and unaligned writes seem to cause a sticky error.
* TODO: it would be nice to have a way to detect whether unaligned
* operations are supported on other processors. */
- dap->unaligned_access_bad = dap->ti_be_32_quirks;
+ ap->unaligned_access_bad = dap->ti_be_32_quirks;
LOG_DEBUG("MEM_AP CFG: large data %d, long address %d, big-endian %d",
!!(cfg & 0x04), !!(cfg & 0x02), !!(cfg & 0x01));
}
int dap_get_debugbase(struct adiv5_dap *dap, int ap,
- uint32_t *out_dbgbase, uint32_t *out_apid)
+ uint32_t *dbgbase, uint32_t *apid)
{
uint32_t ap_old;
int retval;
- uint32_t dbgbase, apid;
/* AP address is in bits 31:24 of DP_SELECT */
if (ap >= 256)
return ERROR_COMMAND_SYNTAX_ERROR;
- ap_old = dap->ap_current;
+ ap_old = dap_ap_get_select(dap);
dap_ap_select(dap, ap);
- retval = dap_queue_ap_read(dap, AP_REG_BASE, &dbgbase);
+ retval = dap_queue_ap_read(dap, MEM_AP_REG_BASE, dbgbase);
if (retval != ERROR_OK)
return retval;
- retval = dap_queue_ap_read(dap, AP_REG_IDR, &apid);
+ retval = dap_queue_ap_read(dap, AP_REG_IDR, apid);
if (retval != ERROR_OK)
return retval;
retval = dap_run(dap);
if (retval != ERROR_OK)
return retval;
- /* Excavate the device ID code */
- struct jtag_tap *tap = dap->jtag_info->tap;
- while (tap != NULL) {
- if (tap->hasidcode)
- break;
- tap = tap->next_tap;
- }
- if (tap == NULL || !tap->hasidcode)
- return ERROR_OK;
-
dap_ap_select(dap, ap_old);
- /* The asignment happens only here to prevent modification of these
- * values before they are certain. */
- *out_dbgbase = dbgbase;
- *out_apid = apid;
-
return ERROR_OK;
}
int dap_lookup_cs_component(struct adiv5_dap *dap, int ap,
- uint32_t dbgbase, uint8_t type, uint32_t *addr)
+ uint32_t dbgbase, uint8_t type, uint32_t *addr, int32_t *idx)
{
uint32_t ap_old;
uint32_t romentry, entry_offset = 0, component_base, devtype;
- int retval = ERROR_FAIL;
+ int retval;
if (ap >= 256)
return ERROR_COMMAND_SYNTAX_ERROR;
- ap_old = dap->ap_current;
+ *addr = 0;
+ ap_old = dap_ap_get_select(dap);
dap_ap_select(dap, ap);
do {
+ (romentry & 0xFFFFF000);
if (romentry & 0x1) {
+ uint32_t c_cid1;
+ retval = mem_ap_read_atomic_u32(dap, component_base | 0xff4, &c_cid1);
+ if (retval != ERROR_OK) {
+ LOG_ERROR("Can't read component with base address 0x%" PRIx32
+ ", the corresponding core might be turned off", component_base);
+ return retval;
+ }
+ if (((c_cid1 >> 4) & 0x0f) == 1) {
+ retval = dap_lookup_cs_component(dap, ap, component_base,
+ type, addr, idx);
+ if (retval == ERROR_OK)
+ break;
+ if (retval != ERROR_TARGET_RESOURCE_NOT_AVAILABLE)
+ return retval;
+ }
+
retval = mem_ap_read_atomic_u32(dap,
(component_base & 0xfffff000) | 0xfcc,
&devtype);
if (retval != ERROR_OK)
return retval;
if ((devtype & 0xff) == type) {
- *addr = component_base;
- retval = ERROR_OK;
- break;
+ if (!*idx) {
+ *addr = component_base;
+ break;
+ } else
+ (*idx)--;
}
}
entry_offset += 4;
dap_ap_select(dap, ap_old);
- return retval;
+ if (!*addr)
+ return ERROR_TARGET_RESOURCE_NOT_AVAILABLE;
+
+ return ERROR_OK;
}
static int dap_rom_display(struct command_context *cmd_ctx,
uint32_t c_cid0, c_cid1, c_cid2, c_cid3;
uint32_t c_pid0, c_pid1, c_pid2, c_pid3, c_pid4;
uint32_t component_base;
- unsigned part_num;
- char *type, *full;
+ uint32_t part_num;
+ const char *type, *full;
component_base = (dbgbase & 0xFFFFF000) + (romentry & 0xFFFFF000);
if (((c_cid1 >> 4) & 0x0f) == 9) {
uint32_t devtype;
unsigned minor;
- char *major = "Reserved", *subtype = "Reserved";
+ const char *major = "Reserved", *subtype = "Reserved";
retval = mem_ap_read_atomic_u32(dap,
(component_base & 0xfffff000) | 0xfcc,
type = "Cortex-M3 FBP";
full = "(Flash Patch and Breakpoint)";
break;
+ case 0x008:
+ type = "Cortex-M0 SCS";
+ full = "(System Control Space)";
+ break;
+ case 0x00a:
+ type = "Cortex-M0 DWT";
+ full = "(Data Watchpoint and Trace)";
+ break;
+ case 0x00b:
+ type = "Cortex-M0 BPU";
+ full = "(Breakpoint Unit)";
+ break;
case 0x00c:
type = "Cortex-M4 SCS";
full = "(System Control Space)";
type = "Coresight ITM";
full = "(Instrumentation Trace Macrocell)";
break;
+ case 0x914:
+ type = "Coresight SWO";
+ full = "(Single Wire Output)";
+ break;
case 0x917:
type = "Coresight HTM";
full = "(AHB Trace Macrocell)";
type = "CoreSight Component";
full = "(unidentified Cortex-A9 component)";
break;
+ case 0x961:
+ type = "CoreSight TMC";
+ full = "(Trace Memory Controller)";
+ break;
case 0x962:
type = "CoreSight STM";
full = "(System Trace Macrocell)";
type = "Cortex-M4 TPUI";
full = "(Trace Port Interface Unit)";
break;
+ case 0x9a5:
+ type = "Cortex-A5 ETM";
+ full = "(Embedded Trace)";
+ break;
+ case 0xc05:
+ type = "Cortex-A5 Debug";
+ full = "(Debug Unit)";
+ break;
case 0xc08:
type = "Cortex-A8 Debug";
full = "(Debug Unit)";
type = "Cortex-A9 Debug";
full = "(Debug Unit)";
break;
+ case 0x4af:
+ type = "Cortex-A15 Debug";
+ full = "(Debug Unit)";
+ break;
default:
+ LOG_DEBUG("Unrecognized Part number 0x%" PRIx32, part_num);
type = "-*- unrecognized -*-";
full = "";
break;
struct adiv5_dap *dap, int ap)
{
int retval;
- uint32_t dbgbase = 0, apid = 0; /* Silence gcc by initializing */
+ uint32_t dbgbase, apid;
int romtable_present = 0;
uint8_t mem_ap;
uint32_t ap_old;
if (retval != ERROR_OK)
return retval;
- ap_old = dap->ap_current;
+ ap_old = dap_ap_get_select(dap);
dap_ap_select(dap, ap);
/* Now we read ROM table ID registers, ref. ARM IHI 0029B sec */
command_print(cmd_ctx, "No AP found at this ap 0x%x", ap);
romtable_present = ((mem_ap) && (dbgbase != 0xFFFFFFFF));
- if (romtable_present) {
+ if (romtable_present)
dap_rom_display(cmd_ctx, dap, ap, dbgbase, 0);
- } else
+ else
command_print(cmd_ctx, "\tNo ROM table present");
dap_ap_select(dap, ap_old);
* though they're not common for now. This should
* use the ID register to verify it's a MEM-AP.
*/
- retval = dap_queue_ap_read(dap, AP_REG_BASE, &baseaddr);
+ retval = dap_queue_ap_read(dap, MEM_AP_REG_BASE, &baseaddr);
if (retval != ERROR_OK)
return retval;
retval = dap_run(dap);
switch (CMD_ARGC) {
case 0:
- memaccess_tck = dap->memaccess_tck;
+ memaccess_tck = dap->ap[dap->apsel].memaccess_tck;
break;
case 1:
COMMAND_PARSE_NUMBER(u32, CMD_ARGV[0], memaccess_tck);
default:
return ERROR_COMMAND_SYNTAX_ERROR;
}
- dap->memaccess_tck = memaccess_tck;
+ dap->ap[dap->apsel].memaccess_tck = memaccess_tck;
command_print(CMD_CTX, "memory bus access delay set to %" PRIi32 " tck",
- dap->memaccess_tck);
+ dap->ap[dap->apsel].memaccess_tck);
return ERROR_OK;
}
struct arm *arm = target_to_arm(target);
struct adiv5_dap *dap = arm->dap;
- uint32_t apcsw = dap->apcsw[dap->apsel], sprot = 0;
+ uint32_t apcsw = dap->ap[dap->apsel].csw_default, sprot = 0;
switch (CMD_ARGC) {
case 0:
default:
return ERROR_COMMAND_SYNTAX_ERROR;
}
- dap->apcsw[dap->apsel] = apcsw;
+ dap->ap[dap->apsel].csw_default = apcsw;
return 0;
}
Code Review / openocd.git / blobdiff