*/
int ahbap_debugport_init(struct adiv5_dap *dap)
{
- uint32_t dummy;
uint32_t ctrlstat;
int cnt = 0;
int retval;
LOG_DEBUG(" ");
- /* JTAG-DP or SWJ-DP, in JTAG mode */
- dap->ops = &jtag_dp_ops;
+ /* JTAG-DP or SWJ-DP, in JTAG mode
+ * ... for SWD mode this is patched as part
+ * of link switchover
+ */
+ if (!dap->ops)
+ dap->ops = &jtag_dp_ops;
/* Default MEM-AP setup.
*
/* DP initialization */
- retval = dap_queue_dp_read(dap, DP_CTRL_STAT, &dummy);
+ retval = dap_queue_dp_read(dap, DP_CTRL_STAT, NULL);
if (retval != ERROR_OK)
return retval;
if (retval != ERROR_OK)
return retval;
- retval = dap_queue_dp_read(dap, DP_CTRL_STAT, &dummy);
+ retval = dap_queue_dp_read(dap, DP_CTRL_STAT, NULL);
if (retval != ERROR_OK)
return retval;
alive_sleep(10);
}
- retval = dap_queue_dp_read(dap, DP_CTRL_STAT, &dummy);
+ retval = dap_queue_dp_read(dap, DP_CTRL_STAT, NULL);
if (retval != ERROR_OK)
return retval;
/* With debug power on we can activate OVERRUN checking */
retval = dap_queue_dp_write(dap, DP_CTRL_STAT, dap->dp_ctrl_stat);
if (retval != ERROR_OK)
return retval;
- retval = dap_queue_dp_read(dap, DP_CTRL_STAT, &dummy);
+ retval = dap_queue_dp_read(dap, DP_CTRL_STAT, NULL);
if (retval != ERROR_OK)
return retval;
struct broken_cpu {
uint32_t dbgbase;
uint32_t apid;
+ uint32_t idcode;
uint32_t correct_dbgbase;
char *model;
} broken_cpus[] = {
- { 0x80000000, 0x04770002, 0x60000000, "imx51" },
+ { 0x80000000, 0x04770002, 0x1ba00477, 0x60000000, "imx51" },
};
int dap_get_debugbase(struct adiv5_dap *dap, int apsel,
uint32_t apselold;
int retval;
unsigned int i;
- uint32_t dbgbase, apid;
+ uint32_t dbgbase, apid, idcode;
/* AP address is in bits 31:24 of DP_SELECT */
if (apsel >= 256)
if (retval != ERROR_OK)
return retval;
+ /* Excavate the device ID code */
+ struct jtag_tap *tap = dap->jtag_info->tap;
+ while (tap != NULL) {
+ if (tap->hasidcode) {
+ idcode = tap->idcode;
+ break;
+ }
+ tap = tap->next_tap;
+ }
+ if (tap == NULL || !tap->hasidcode)
+ return ERROR_OK;
+
/* Some CPUs are messed up, so fixup if needed. */
for (i = 0; i < sizeof(broken_cpus)/sizeof(struct broken_cpu); i++)
if (broken_cpus[i].dbgbase == dbgbase &&
- broken_cpus[i].apid == apid) {
+ broken_cpus[i].apid == apid &&
+ broken_cpus[i].idcode == idcode) {
LOG_WARNING("Found broken CPU (%s), trying to fixup "
"ROM Table location from 0x%08x to 0x%08x",
broken_cpus[i].model, dbgbase,
/* Part number interpretations are from Cortex
* core specs, the CoreSight components TRM
- * (ARM DDI 0314H), and ETM specs; also from
- * chip observation (e.g. TI SDTI).
+ * (ARM DDI 0314H), CoreSight System Design
+ * Guide (ARM DGI 0012D) and ETM specs; also
+ * from chip observation (e.g. TI SDTI).
*/
part_num = (c_pid0 & 0xff);
part_num |= (c_pid1 & 0x0f) << 8;
type = "Cortex-M3 ETM";
full = "(Embedded Trace)";
break;
+ case 0x930:
+ type = "Cortex-R4 ETM";
+ full = "(Embedded Trace)";
+ break;
case 0xc08:
type = "Cortex-A8 Debug";
full = "(Debug Unit)";