/* ARM ADI Specification requires at least 10 bits used for TAR autoincrement */
/*
- u32 tar_block_size(u32 address)
+ uint32_t tar_block_size(uint32_t address)
Return the largest block starting at address that does not cross a tar block size alignment boundary
*/
-static u32 max_tar_block_size(u32 tar_autoincr_block, u32 address)
+static uint32_t max_tar_block_size(uint32_t tar_autoincr_block, uint32_t address)
{
return (tar_autoincr_block - ((tar_autoincr_block - 1) & address)) >> 2;
}
return ERROR_OK;
}
-/* Scan out and in from host ordered u32 variables */
-int adi_jtag_dp_scan_u32(swjdp_common_t *swjdp, uint8_t instr, uint8_t reg_addr, uint8_t RnW, u32 outvalue, u32 *invalue, uint8_t *ack)
+/* Scan out and in from host ordered uint32_t variables */
+int adi_jtag_dp_scan_u32(swjdp_common_t *swjdp, uint8_t instr, uint8_t reg_addr, uint8_t RnW, uint32_t outvalue, uint32_t *invalue, uint8_t *ack)
{
arm_jtag_t *jtag_info = swjdp->jtag_info;
scan_field_t fields[2];
fields[1].in_value = (uint8_t *)invalue;
jtag_add_dr_scan(2, fields, jtag_get_end_state());
- jtag_add_callback(arm_le_to_h_u32, (uint8_t *)invalue);
+ jtag_add_callback(arm_le_to_h_u32, (jtag_callback_data_t) invalue);
} else
{
adi_jtag_dp_scan(swjdp, DAP_IR_DPACC, DP_RDBUFF, DPAP_READ, 0, invalue, &swjdp->ack);
}
- /* In TRANS_MODE_ATOMIC all DAP_IR_APACC transactions wait for ack=OK/FAULT and the check CTRL_STAT */
+ /* In TRANS_MODE_ATOMIC all DAP_IR_APACC transactions wait for ack = OK/FAULT and the check CTRL_STAT */
if ((instr == DAP_IR_APACC) && (swjdp->trans_mode == TRANS_MODE_ATOMIC))
{
return swjdp_transaction_endcheck(swjdp);
return ERROR_OK;
}
-int scan_inout_check_u32(swjdp_common_t *swjdp, uint8_t instr, uint8_t reg_addr, uint8_t RnW, u32 outvalue, u32 *invalue)
+int scan_inout_check_u32(swjdp_common_t *swjdp, uint8_t instr, uint8_t reg_addr, uint8_t RnW, uint32_t outvalue, uint32_t *invalue)
{
adi_jtag_dp_scan_u32(swjdp, instr, reg_addr, RnW, outvalue, NULL, NULL);
- if ((RnW==DPAP_READ) && (invalue != NULL))
+ if ((RnW == DPAP_READ) && (invalue != NULL))
{
adi_jtag_dp_scan_u32(swjdp, DAP_IR_DPACC, DP_RDBUFF, DPAP_READ, 0, invalue, &swjdp->ack);
}
- /* In TRANS_MODE_ATOMIC all DAP_IR_APACC transactions wait for ack=OK/FAULT and then check CTRL_STAT */
+ /* In TRANS_MODE_ATOMIC all DAP_IR_APACC transactions wait for ack = OK/FAULT and then check CTRL_STAT */
if ((instr == DAP_IR_APACC) && (swjdp->trans_mode == TRANS_MODE_ATOMIC))
{
return swjdp_transaction_endcheck(swjdp);
int swjdp_transaction_endcheck(swjdp_common_t *swjdp)
{
int retval;
- u32 ctrlstat;
+ uint32_t ctrlstat;
/* too expensive to call keep_alive() here */
https://lists.berlios.de/pipermail/openocd-development/2008-September/003107.html
*/
- if ((retval=jtag_execute_queue())!=ERROR_OK)
+ if ((retval = jtag_execute_queue()) != ERROR_OK)
{
LOG_ERROR("BUG: Why does this fail the first time????");
}
#endif
scan_inout_check_u32(swjdp, DAP_IR_DPACC, DP_CTRL_STAT, DPAP_READ, 0, &ctrlstat);
- if ((retval=jtag_execute_queue())!=ERROR_OK)
+ if ((retval = jtag_execute_queue()) != ERROR_OK)
return retval;
swjdp->ack = swjdp->ack & 0x7;
if (swjdp->ack != 2)
{
- long long then=timeval_ms();
+ long long then = timeval_ms();
while (swjdp->ack != 2)
{
if (swjdp->ack == 1)
}
scan_inout_check_u32(swjdp, DAP_IR_DPACC, DP_CTRL_STAT, DPAP_READ, 0, &ctrlstat);
- if ((retval=jtag_execute_queue())!=ERROR_OK)
+ if ((retval = jtag_execute_queue()) != ERROR_OK)
return retval;
swjdp->ack = swjdp->ack & 0x7;
}
/* Check for STICKYERR and STICKYORUN */
if (ctrlstat & (SSTICKYORUN | SSTICKYERR))
{
- LOG_DEBUG("swjdp: CTRL/STAT error 0x%x", ctrlstat);
+ LOG_DEBUG("swjdp: CTRL/STAT error 0x%" PRIx32 "", ctrlstat);
/* Check power to debug regions */
if ((ctrlstat & 0xf0000000) != 0xf0000000)
{
}
else
{
- u32 mem_ap_csw, mem_ap_tar;
+ uint32_t mem_ap_csw, mem_ap_tar;
/* Print information about last AHBAP access */
- LOG_ERROR("AHBAP Cached values: dp_select 0x%x, ap_csw 0x%x, ap_tar 0x%x", swjdp->dp_select_value, swjdp->ap_csw_value, swjdp->ap_tar_value);
+ LOG_ERROR("AHBAP Cached values: dp_select 0x%" PRIx32 ", ap_csw 0x%" PRIx32 ", ap_tar 0x%" PRIx32 "", swjdp->dp_select_value, swjdp->ap_csw_value, swjdp->ap_tar_value);
if (ctrlstat & SSTICKYORUN)
LOG_ERROR("SWJ-DP OVERRUN - check clock or reduce jtag speed");
/* Clear Sticky Error Bits */
scan_inout_check_u32(swjdp, DAP_IR_DPACC, DP_CTRL_STAT, DPAP_WRITE, swjdp->dp_ctrl_stat | SSTICKYORUN | SSTICKYERR, NULL);
scan_inout_check_u32(swjdp, DAP_IR_DPACC, DP_CTRL_STAT, DPAP_READ, 0, &ctrlstat);
- if ((retval=jtag_execute_queue())!=ERROR_OK)
+ if ((retval = jtag_execute_queue()) != ERROR_OK)
return retval;
- LOG_DEBUG("swjdp: status 0x%x", ctrlstat);
+ LOG_DEBUG("swjdp: status 0x%" PRIx32 "", ctrlstat);
dap_ap_read_reg_u32(swjdp, AP_REG_CSW, &mem_ap_csw);
dap_ap_read_reg_u32(swjdp, AP_REG_TAR, &mem_ap_tar);
- if ((retval=jtag_execute_queue())!=ERROR_OK)
+ if ((retval = jtag_execute_queue()) != ERROR_OK)
return retval;
- LOG_ERROR("Read MEM_AP_CSW 0x%x, MEM_AP_TAR 0x%x", mem_ap_csw, mem_ap_tar);
+ LOG_ERROR("Read MEM_AP_CSW 0x%" PRIx32 ", MEM_AP_TAR 0x%" PRIx32 "", mem_ap_csw, mem_ap_tar);
}
- if ((retval=jtag_execute_queue())!=ERROR_OK)
+ if ((retval = jtag_execute_queue()) != ERROR_OK)
return retval;
return ERROR_JTAG_DEVICE_ERROR;
}
* *
***************************************************************************/
-int dap_dp_write_reg(swjdp_common_t *swjdp, u32 value, uint8_t reg_addr)
+int dap_dp_write_reg(swjdp_common_t *swjdp, uint32_t value, uint8_t reg_addr)
{
return scan_inout_check_u32(swjdp, DAP_IR_DPACC, reg_addr, DPAP_WRITE, value, NULL);
}
-int dap_dp_read_reg(swjdp_common_t *swjdp, u32 *value, uint8_t reg_addr)
+int dap_dp_read_reg(swjdp_common_t *swjdp, uint32_t *value, uint8_t reg_addr)
{
return scan_inout_check_u32(swjdp, DAP_IR_DPACC, reg_addr, DPAP_READ, 0, value);
}
int dap_ap_select(swjdp_common_t *swjdp,uint8_t apsel)
{
- u32 select;
- select = (apsel<<24) & 0xFF000000;
+ uint32_t select;
+ select = (apsel << 24) & 0xFF000000;
if (select != swjdp->apsel)
{
return ERROR_OK;
}
-int dap_dp_bankselect(swjdp_common_t *swjdp,u32 ap_reg)
+int dap_dp_bankselect(swjdp_common_t *swjdp,uint32_t ap_reg)
{
- u32 select;
+ uint32_t select;
select = (ap_reg & 0x000000F0);
if (select != swjdp->dp_select_value)
return ERROR_OK;
}
-int dap_ap_write_reg(swjdp_common_t *swjdp, u32 reg_addr, uint8_t* out_value_buf)
+int dap_ap_write_reg(swjdp_common_t *swjdp, uint32_t reg_addr, uint8_t* out_value_buf)
{
dap_dp_bankselect(swjdp, reg_addr);
scan_inout_check(swjdp, DAP_IR_APACC, reg_addr, DPAP_WRITE, out_value_buf, NULL);
return ERROR_OK;
}
-int dap_ap_read_reg(swjdp_common_t *swjdp, u32 reg_addr, uint8_t *in_value_buf)
+int dap_ap_read_reg(swjdp_common_t *swjdp, uint32_t reg_addr, uint8_t *in_value_buf)
{
dap_dp_bankselect(swjdp, reg_addr);
scan_inout_check(swjdp, DAP_IR_APACC, reg_addr, DPAP_READ, 0, in_value_buf);
return ERROR_OK;
}
-int dap_ap_write_reg_u32(swjdp_common_t *swjdp, u32 reg_addr, u32 value)
+int dap_ap_write_reg_u32(swjdp_common_t *swjdp, uint32_t reg_addr, uint32_t value)
{
uint8_t out_value_buf[4];
return ERROR_OK;
}
-int dap_ap_read_reg_u32(swjdp_common_t *swjdp, u32 reg_addr, u32 *value)
+int dap_ap_read_reg_u32(swjdp_common_t *swjdp, uint32_t reg_addr, uint32_t *value)
{
dap_dp_bankselect(swjdp, reg_addr);
scan_inout_check_u32(swjdp, DAP_IR_APACC, reg_addr, DPAP_READ, 0, value);
* *
***************************************************************************/
-int dap_setup_accessport(swjdp_common_t *swjdp, u32 csw, u32 tar)
+int dap_setup_accessport(swjdp_common_t *swjdp, uint32_t csw, uint32_t tar)
{
csw = csw | CSW_DBGSWENABLE | CSW_MASTER_DEBUG | CSW_HPROT;
if (csw != swjdp->ap_csw_value)
/*****************************************************************************
* *
-* mem_ap_read_u32(swjdp_common_t *swjdp, u32 address, u32 *value) *
+* mem_ap_read_u32(swjdp_common_t *swjdp, uint32_t address, uint32_t *value) *
* *
-* Read a u32 value from memory or system register *
-* Functionally equivalent to target_read_u32(target, address, u32 *value), *
+* Read a uint32_t value from memory or system register *
+* Functionally equivalent to target_read_u32(target, address, uint32_t *value), *
* but with less overhead *
*****************************************************************************/
-int mem_ap_read_u32(swjdp_common_t *swjdp, u32 address, u32 *value)
+int mem_ap_read_u32(swjdp_common_t *swjdp, uint32_t address, uint32_t *value)
{
swjdp->trans_mode = TRANS_MODE_COMPOSITE;
return ERROR_OK;
}
-int mem_ap_read_atomic_u32(swjdp_common_t *swjdp, u32 address, u32 *value)
+int mem_ap_read_atomic_u32(swjdp_common_t *swjdp, uint32_t address, uint32_t *value)
{
mem_ap_read_u32(swjdp, address, value);
/*****************************************************************************
* *
-* mem_ap_write_u32(swjdp_common_t *swjdp, u32 address, u32 value) *
+* mem_ap_write_u32(swjdp_common_t *swjdp, uint32_t address, uint32_t value) *
* *
-* Write a u32 value to memory or memory mapped register *
+* Write a uint32_t value to memory or memory mapped register *
* *
*****************************************************************************/
-int mem_ap_write_u32(swjdp_common_t *swjdp, u32 address, u32 value)
+int mem_ap_write_u32(swjdp_common_t *swjdp, uint32_t address, uint32_t value)
{
swjdp->trans_mode = TRANS_MODE_COMPOSITE;
return ERROR_OK;
}
-int mem_ap_write_atomic_u32(swjdp_common_t *swjdp, u32 address, u32 value)
+int mem_ap_write_atomic_u32(swjdp_common_t *swjdp, uint32_t address, uint32_t value)
{
mem_ap_write_u32(swjdp, address, value);
/*****************************************************************************
* *
-* mem_ap_write_buf(swjdp_common_t *swjdp, uint8_t *buffer, int count, u32 address) *
+* mem_ap_write_buf(swjdp_common_t *swjdp, uint8_t *buffer, int count, uint32_t address) *
* *
* Write a buffer in target order (little endian) *
* *
*****************************************************************************/
-int mem_ap_write_buf_u32(swjdp_common_t *swjdp, uint8_t *buffer, int count, u32 address)
+int mem_ap_write_buf_u32(swjdp_common_t *swjdp, uint8_t *buffer, int count, uint32_t address)
{
int wcount, blocksize, writecount, errorcount = 0, retval = ERROR_OK;
- u32 adr = address;
+ uint32_t adr = address;
uint8_t* pBuffer = buffer;
swjdp->trans_mode = TRANS_MODE_COMPOSITE;
for (writecount = 0; writecount < count; writecount++)
{
int i;
- u32 outvalue;
- memcpy(&outvalue, pBuffer, sizeof(u32));
+ uint32_t outvalue;
+ memcpy(&outvalue, pBuffer, sizeof(uint32_t));
for (i = 0; i < 4; i++ )
{
outvalue >>= 8;
adr++;
}
- pBuffer += sizeof(u32);
+ pBuffer += sizeof(uint32_t);
}
}
if (errorcount > 1)
{
- LOG_WARNING("Block write error address 0x%x, wcount 0x%x", address, wcount);
+ LOG_WARNING("Block write error address 0x%" PRIx32 ", wcount 0x%x", address, wcount);
return ERROR_JTAG_DEVICE_ERROR;
}
}
return retval;
}
-int mem_ap_write_buf_packed_u16(swjdp_common_t *swjdp, uint8_t *buffer, int count, u32 address)
+int mem_ap_write_buf_packed_u16(swjdp_common_t *swjdp, uint8_t *buffer, int count, uint32_t address)
{
int retval = ERROR_OK;
int wcount, blocksize, writecount, i;
{
if (mem_ap_write_buf_u16(swjdp, buffer, nbytes, address) != ERROR_OK)
{
- LOG_WARNING("Block read error address 0x%x, count 0x%x", address, count);
+ LOG_WARNING("Block read error address 0x%" PRIx32 ", count 0x%x", address, count);
return ERROR_JTAG_DEVICE_ERROR;
}
}
else
{
- u32 outvalue;
- memcpy(&outvalue, buffer, sizeof(u32));
+ uint32_t outvalue;
+ memcpy(&outvalue, buffer, sizeof(uint32_t));
for (i = 0; i < nbytes; i++ )
{
address++;
}
- memcpy(&outvalue, buffer, sizeof(u32));
+ memcpy(&outvalue, buffer, sizeof(uint32_t));
dap_ap_write_reg_u32(swjdp, AP_REG_DRW, outvalue);
if (swjdp_transaction_endcheck(swjdp) != ERROR_OK)
{
- LOG_WARNING("Block read error address 0x%x, count 0x%x", address, count);
+ LOG_WARNING("Block read error address 0x%" PRIx32 ", count 0x%x", address, count);
return ERROR_JTAG_DEVICE_ERROR;
}
}
return retval;
}
-int mem_ap_write_buf_u16(swjdp_common_t *swjdp, uint8_t *buffer, int count, u32 address)
+int mem_ap_write_buf_u16(swjdp_common_t *swjdp, uint8_t *buffer, int count, uint32_t address)
{
int retval = ERROR_OK;
while (count > 0)
{
dap_setup_accessport(swjdp, CSW_16BIT | CSW_ADDRINC_SINGLE, address);
- u16 svalue;
- memcpy(&svalue, buffer, sizeof(u16));
- u32 outvalue = (u32)svalue << 8 * (address & 0x3);
+ uint16_t svalue;
+ memcpy(&svalue, buffer, sizeof(uint16_t));
+ uint32_t outvalue = (uint32_t)svalue << 8 * (address & 0x3);
dap_ap_write_reg_u32(swjdp, AP_REG_DRW, outvalue );
retval = swjdp_transaction_endcheck(swjdp);
count -= 2;
return retval;
}
-int mem_ap_write_buf_packed_u8(swjdp_common_t *swjdp, uint8_t *buffer, int count, u32 address)
+int mem_ap_write_buf_packed_u8(swjdp_common_t *swjdp, uint8_t *buffer, int count, uint32_t address)
{
int retval = ERROR_OK;
int wcount, blocksize, writecount, i;
{
if (mem_ap_write_buf_u8(swjdp, buffer, nbytes, address) != ERROR_OK)
{
- LOG_WARNING("Block read error address 0x%x, count 0x%x", address, count);
+ LOG_WARNING("Block read error address 0x%" PRIx32 ", count 0x%x", address, count);
return ERROR_JTAG_DEVICE_ERROR;
}
}
else
{
- u32 outvalue;
- memcpy(&outvalue, buffer, sizeof(u32));
+ uint32_t outvalue;
+ memcpy(&outvalue, buffer, sizeof(uint32_t));
for (i = 0; i < nbytes; i++ )
{
address++;
}
- memcpy(&outvalue, buffer, sizeof(u32));
+ memcpy(&outvalue, buffer, sizeof(uint32_t));
dap_ap_write_reg_u32(swjdp, AP_REG_DRW, outvalue);
if (swjdp_transaction_endcheck(swjdp) != ERROR_OK)
{
- LOG_WARNING("Block read error address 0x%x, count 0x%x", address, count);
+ LOG_WARNING("Block read error address 0x%" PRIx32 ", count 0x%x", address, count);
return ERROR_JTAG_DEVICE_ERROR;
}
}
return retval;
}
-int mem_ap_write_buf_u8(swjdp_common_t *swjdp, uint8_t *buffer, int count, u32 address)
+int mem_ap_write_buf_u8(swjdp_common_t *swjdp, uint8_t *buffer, int count, uint32_t address)
{
int retval = ERROR_OK;
while (count > 0)
{
dap_setup_accessport(swjdp, CSW_8BIT | CSW_ADDRINC_SINGLE, address);
- u32 outvalue = (u32)*buffer << 8 * (address & 0x3);
+ uint32_t outvalue = (uint32_t)*buffer << 8 * (address & 0x3);
dap_ap_write_reg_u32(swjdp, AP_REG_DRW, outvalue );
retval = swjdp_transaction_endcheck(swjdp);
count--;
/*********************************************************************************
* *
-* mem_ap_read_buf_u32(swjdp_common_t *swjdp, uint8_t *buffer, int count, u32 address) *
+* mem_ap_read_buf_u32(swjdp_common_t *swjdp, uint8_t *buffer, int count, uint32_t address) *
* *
* Read block fast in target order (little endian) into a buffer *
* *
**********************************************************************************/
-int mem_ap_read_buf_u32(swjdp_common_t *swjdp, uint8_t *buffer, int count, u32 address)
+int mem_ap_read_buf_u32(swjdp_common_t *swjdp, uint8_t *buffer, int count, uint32_t address)
{
int wcount, blocksize, readcount, errorcount = 0, retval = ERROR_OK;
- u32 adr = address;
+ uint32_t adr = address;
uint8_t* pBuffer = buffer;
swjdp->trans_mode = TRANS_MODE_COMPOSITE;
if (errorcount > 1)
{
- LOG_WARNING("Block read error address 0x%x, count 0x%x", address, count);
+ LOG_WARNING("Block read error address 0x%" PRIx32 ", count 0x%x", address, count);
return ERROR_JTAG_DEVICE_ERROR;
}
}
for (readcount = 0; readcount < count; readcount++)
{
int i;
- u32 data;
- memcpy(&data, pBuffer, sizeof(u32));
+ uint32_t data;
+ memcpy(&data, pBuffer, sizeof(uint32_t));
for (i = 0; i < 4; i++ )
{
return retval;
}
-int mem_ap_read_buf_packed_u16(swjdp_common_t *swjdp, uint8_t *buffer, int count, u32 address)
+int mem_ap_read_buf_packed_u16(swjdp_common_t *swjdp, uint8_t *buffer, int count, uint32_t address)
{
- u32 invalue;
+ uint32_t invalue;
int retval = ERROR_OK;
int wcount, blocksize, readcount, i;
dap_ap_read_reg_u32(swjdp, AP_REG_DRW, &invalue );
if (swjdp_transaction_endcheck(swjdp) != ERROR_OK)
{
- LOG_WARNING("Block read error address 0x%x, count 0x%x", address, count);
+ LOG_WARNING("Block read error address 0x%" PRIx32 ", count 0x%x", address, count);
return ERROR_JTAG_DEVICE_ERROR;
}
return retval;
}
-int mem_ap_read_buf_u16(swjdp_common_t *swjdp, uint8_t *buffer, int count, u32 address)
+int mem_ap_read_buf_u16(swjdp_common_t *swjdp, uint8_t *buffer, int count, uint32_t address)
{
- u32 invalue, i;
+ uint32_t invalue, i;
int retval = ERROR_OK;
if (count >= 4)
}
else
{
- u16 svalue = (invalue >> 8 * (address & 0x3));
- memcpy(buffer, &svalue, sizeof(u16));
+ uint16_t svalue = (invalue >> 8 * (address & 0x3));
+ memcpy(buffer, &svalue, sizeof(uint16_t));
address += 2;
buffer += 2;
}
* The solution is to arrange for a large out/in scan in this loop and
* and convert data afterwards.
*/
-int mem_ap_read_buf_packed_u8(swjdp_common_t *swjdp, uint8_t *buffer, int count, u32 address)
+int mem_ap_read_buf_packed_u8(swjdp_common_t *swjdp, uint8_t *buffer, int count, uint32_t address)
{
- u32 invalue;
+ uint32_t invalue;
int retval = ERROR_OK;
int wcount, blocksize, readcount, i;
dap_ap_read_reg_u32(swjdp, AP_REG_DRW, &invalue );
if (swjdp_transaction_endcheck(swjdp) != ERROR_OK)
{
- LOG_WARNING("Block read error address 0x%x, count 0x%x", address, count);
+ LOG_WARNING("Block read error address 0x%" PRIx32 ", count 0x%x", address, count);
return ERROR_JTAG_DEVICE_ERROR;
}
return retval;
}
-int mem_ap_read_buf_u8(swjdp_common_t *swjdp, uint8_t *buffer, int count, u32 address)
+int mem_ap_read_buf_u8(swjdp_common_t *swjdp, uint8_t *buffer, int count, uint32_t address)
{
- u32 invalue;
+ uint32_t invalue;
int retval = ERROR_OK;
if (count >= 4)
int ahbap_debugport_init(swjdp_common_t *swjdp)
{
- u32 idreg, romaddr, dummy;
- u32 ctrlstat;
+ uint32_t idreg, romaddr, dummy;
+ uint32_t ctrlstat;
int cnt = 0;
int retval;
dap_dp_write_reg(swjdp, swjdp->dp_ctrl_stat, DP_CTRL_STAT);
dap_dp_read_reg(swjdp, &ctrlstat, DP_CTRL_STAT);
- if ((retval=jtag_execute_queue())!=ERROR_OK)
+ if ((retval = jtag_execute_queue()) != ERROR_OK)
return retval;
/* Check that we have debug power domains activated */
{
LOG_DEBUG("swjdp: wait CDBGPWRUPACK");
dap_dp_read_reg(swjdp, &ctrlstat, DP_CTRL_STAT);
- if ((retval=jtag_execute_queue())!=ERROR_OK)
+ if ((retval = jtag_execute_queue()) != ERROR_OK)
return retval;
alive_sleep(10);
}
{
LOG_DEBUG("swjdp: wait CSYSPWRUPACK");
dap_dp_read_reg(swjdp, &ctrlstat, DP_CTRL_STAT);
- if ((retval=jtag_execute_queue())!=ERROR_OK)
+ if ((retval = jtag_execute_queue()) != ERROR_OK)
return retval;
alive_sleep(10);
}
dap_ap_read_reg_u32(swjdp, 0xFC, &idreg);
dap_ap_read_reg_u32(swjdp, 0xF8, &romaddr);
- LOG_DEBUG("AHB-AP ID Register 0x%x, Debug ROM Address 0x%x", idreg, romaddr);
+ LOG_DEBUG("AHB-AP ID Register 0x%" PRIx32 ", Debug ROM Address 0x%" PRIx32 "", idreg, romaddr);
return ERROR_OK;
}
int dap_info_command(struct command_context_s *cmd_ctx, swjdp_common_t *swjdp, int apsel)
{
- u32 dbgbase,apid;
+ uint32_t dbgbase,apid;
int romtable_present = 0;
uint8_t mem_ap;
- u32 apselold;
+ uint32_t apselold;
apselold = swjdp->apsel;
dap_ap_select(swjdp, apsel);
dap_ap_read_reg_u32(swjdp, 0xFC, &apid);
swjdp_transaction_endcheck(swjdp);
/* Now we read ROM table ID registers, ref. ARM IHI 0029B sec */
- mem_ap = ((apid&0x10000)&&((apid&0x0F)!=0));
- command_print(cmd_ctx, "ap identification register 0x%8.8x", apid);
+ mem_ap = ((apid&0x10000) && ((apid&0x0F) != 0));
+ command_print(cmd_ctx, "ap identification register 0x%8.8" PRIx32 "", apid);
if (apid)
{
switch (apid&0x0F)
command_print(cmd_ctx, "\tUnknown AP-type");
break;
}
- command_print(cmd_ctx, "ap debugbase 0x%8.8x", dbgbase);
+ command_print(cmd_ctx, "ap debugbase 0x%8.8" PRIx32 "", dbgbase);
}
else
{
command_print(cmd_ctx, "No AP found at this apsel 0x%x", apsel);
}
- romtable_present = ((mem_ap)&&(dbgbase != 0xFFFFFFFF));
+ romtable_present = ((mem_ap) && (dbgbase != 0xFFFFFFFF));
if (romtable_present)
{
- u32 cid0,cid1,cid2,cid3,memtype,romentry;
- u16 entry_offset;
+ uint32_t cid0,cid1,cid2,cid3,memtype,romentry;
+ uint16_t entry_offset;
/* bit 16 of apid indicates a memory access port */
if (dbgbase&0x02)
{
command_print(cmd_ctx, "\tROM table in legacy format" );
}
/* Now we read ROM table ID registers, ref. ARM IHI 0029B sec */
- mem_ap_read_u32(swjdp, (dbgbase&0xFFFFF000)|0xFF0, &cid0);
- mem_ap_read_u32(swjdp, (dbgbase&0xFFFFF000)|0xFF4, &cid1);
- mem_ap_read_u32(swjdp, (dbgbase&0xFFFFF000)|0xFF8, &cid2);
- mem_ap_read_u32(swjdp, (dbgbase&0xFFFFF000)|0xFFC, &cid3);
- mem_ap_read_u32(swjdp, (dbgbase&0xFFFFF000)|0xFCC, &memtype);
+ mem_ap_read_u32(swjdp, (dbgbase&0xFFFFF000) | 0xFF0, &cid0);
+ mem_ap_read_u32(swjdp, (dbgbase&0xFFFFF000) | 0xFF4, &cid1);
+ mem_ap_read_u32(swjdp, (dbgbase&0xFFFFF000) | 0xFF8, &cid2);
+ mem_ap_read_u32(swjdp, (dbgbase&0xFFFFF000) | 0xFFC, &cid3);
+ mem_ap_read_u32(swjdp, (dbgbase&0xFFFFF000) | 0xFCC, &memtype);
swjdp_transaction_endcheck(swjdp);
- command_print(cmd_ctx, "\tCID3 0x%x, CID2 0x%x, CID1 0x%x, CID0, 0x%x",cid3,cid2,cid1,cid0);
+ command_print(cmd_ctx, "\tCID3 0x%" PRIx32 ", CID2 0x%" PRIx32 ", CID1 0x%" PRIx32 " CID0, 0x%" PRIx32,cid3,cid2,cid1,cid0);
if (memtype&0x01)
{
command_print(cmd_ctx, "\tMEMTYPE system memory present on bus");
command_print(cmd_ctx, "\tMEMTYPE system memory not present. Dedicated debug bus" );
}
- /* Now we read ROM table entries from dbgbase&0xFFFFF000)|0x000 until we get 0x00000000 */
+ /* Now we read ROM table entries from dbgbase&0xFFFFF000) | 0x000 until we get 0x00000000 */
entry_offset = 0;
do
{
- mem_ap_read_atomic_u32(swjdp, (dbgbase&0xFFFFF000)|entry_offset, &romentry);
- command_print(cmd_ctx, "\tROMTABLE[0x%x] = 0x%x",entry_offset,romentry);
+ mem_ap_read_atomic_u32(swjdp, (dbgbase&0xFFFFF000) | entry_offset, &romentry);
+ command_print(cmd_ctx, "\tROMTABLE[0x%x] = 0x%" PRIx32 "",entry_offset,romentry);
if (romentry&0x01)
{
- u32 c_cid0,c_cid1,c_cid2,c_cid3,c_pid0,c_pid1,c_pid2,c_pid3,c_pid4,component_start;
- u32 component_base = (u32)((dbgbase&0xFFFFF000)+(int)(romentry&0xFFFFF000));
- mem_ap_read_atomic_u32(swjdp, (component_base&0xFFFFF000)|0xFE0, &c_pid0);
- mem_ap_read_atomic_u32(swjdp, (component_base&0xFFFFF000)|0xFE4, &c_pid1);
- mem_ap_read_atomic_u32(swjdp, (component_base&0xFFFFF000)|0xFE8, &c_pid2);
- mem_ap_read_atomic_u32(swjdp, (component_base&0xFFFFF000)|0xFEC, &c_pid3);
- mem_ap_read_atomic_u32(swjdp, (component_base&0xFFFFF000)|0xFD0, &c_pid4);
- mem_ap_read_atomic_u32(swjdp, (component_base&0xFFFFF000)|0xFF0, &c_cid0);
- mem_ap_read_atomic_u32(swjdp, (component_base&0xFFFFF000)|0xFF4, &c_cid1);
- mem_ap_read_atomic_u32(swjdp, (component_base&0xFFFFF000)|0xFF8, &c_cid2);
- mem_ap_read_atomic_u32(swjdp, (component_base&0xFFFFF000)|0xFFC, &c_cid3);
- component_start = component_base - 0x1000*(c_pid4>>4);
- command_print(cmd_ctx, "\t\tComponent base address 0x%x, pid4 0x%x, start address 0x%x",component_base,c_pid4,component_start);
- command_print(cmd_ctx, "\t\tComponent cid1 0x%x, class is %s",c_cid1,class_description[(c_cid1>>4)&0xF]); /* Se ARM DDI 0314 C Table 2.2 */
- command_print(cmd_ctx, "\t\tCID3 0x%x, CID2 0x%x, CID1 0x%x, CID0, 0x%x",c_cid3,c_cid2,c_cid1,c_cid0);
- command_print(cmd_ctx, "\t\tPID3 0x%x, PID2 0x%x, PID1 0x%x, PID0, 0x%x",c_pid3,c_pid2,c_pid1,c_pid0);
- /* For CoreSight components, (c_cid1>>4)&0xF==9 , we also read 0xFC8 DevId and 0xFCC DevType */
+ uint32_t c_cid0,c_cid1,c_cid2,c_cid3,c_pid0,c_pid1,c_pid2,c_pid3,c_pid4,component_start;
+ uint32_t component_base = (uint32_t)((dbgbase&0xFFFFF000) + (int)(romentry&0xFFFFF000));
+ mem_ap_read_atomic_u32(swjdp, (component_base&0xFFFFF000) | 0xFE0, &c_pid0);
+ mem_ap_read_atomic_u32(swjdp, (component_base&0xFFFFF000) | 0xFE4, &c_pid1);
+ mem_ap_read_atomic_u32(swjdp, (component_base&0xFFFFF000) | 0xFE8, &c_pid2);
+ mem_ap_read_atomic_u32(swjdp, (component_base&0xFFFFF000) | 0xFEC, &c_pid3);
+ mem_ap_read_atomic_u32(swjdp, (component_base&0xFFFFF000) | 0xFD0, &c_pid4);
+ mem_ap_read_atomic_u32(swjdp, (component_base&0xFFFFF000) | 0xFF0, &c_cid0);
+ mem_ap_read_atomic_u32(swjdp, (component_base&0xFFFFF000) | 0xFF4, &c_cid1);
+ mem_ap_read_atomic_u32(swjdp, (component_base&0xFFFFF000) | 0xFF8, &c_cid2);
+ mem_ap_read_atomic_u32(swjdp, (component_base&0xFFFFF000) | 0xFFC, &c_cid3);
+ component_start = component_base - 0x1000*(c_pid4 >> 4);
+ command_print(cmd_ctx, "\t\tComponent base address 0x%" PRIx32 ", pid4 0x%" PRIx32 ", start address 0x%" PRIx32 "",component_base,c_pid4,component_start);
+ command_print(cmd_ctx, "\t\tComponent cid1 0x%" PRIx32 ", class is %s",c_cid1,class_description[(c_cid1 >> 4)&0xF]); /* Se ARM DDI 0314 C Table 2.2 */
+ command_print(cmd_ctx, "\t\tCID3 0x%" PRIx32 ", CID2 0x%" PRIx32 ", CID1 0x%" PRIx32 ", CID0, 0x%" PRIx32 "",c_cid3,c_cid2,c_cid1,c_cid0);
+ command_print(cmd_ctx, "\t\tPID3 0x%" PRIx32 ", PID2 0x%" PRIx32 ", PID1 0x%" PRIx32 ", PID0, 0x%" PRIx32 "",c_pid3,c_pid2,c_pid1,c_pid0);
+ /* For CoreSight components, (c_cid1 >> 4)&0xF == 9 , we also read 0xFC8 DevId and 0xFCC DevType */
}
else
{
command_print(cmd_ctx, "\t\tEnd of ROM table");
}
entry_offset += 4;
- } while (romentry>0);
+ } while (romentry > 0);
}
else
{
Code Review / openocd.git / blobdiff