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- fixed arm926 cp15 command bug (thanks to Vincent Palatin for this patch)
[openocd.git] / src / target / arm9tdmi.c
diff --git a/src/target/arm9tdmi.c b/src/target/arm9tdmi.c
index c99fcb2a5c59a2ed4004e4f3c5fcbfe9f5158b07..e3302cf686d30c36c5dafbfb311c8a2393eb9185 100644 (file)
--- a/src/target/arm9tdmi.c
+++ b/src/target/arm9tdmi.c
@@ -28,6 +28,8 @@
 #include "target.h"
 #include "armv4_5.h"
 #include "embeddedice.h"
 #include "target.h"
 #include "armv4_5.h"
 #include "embeddedice.h"
+#include "etm.h"
+#include "etb.h"
 #include "log.h"
 #include "jtag.h"
 #include "arm_jtag.h"
 #include "log.h"
 #include "jtag.h"
 #include "arm_jtag.h"
@@ -68,6 +70,8 @@ target_type_t arm9tdmi_target =
        .write_memory = arm7_9_write_memory,
        .bulk_write_memory = arm7_9_bulk_write_memory,
 
        .write_memory = arm7_9_write_memory,
        .bulk_write_memory = arm7_9_bulk_write_memory,
 
+       .run_algorithm = armv4_5_run_algorithm,
+       
        .add_breakpoint = arm7_9_add_breakpoint,
        .remove_breakpoint = arm7_9_remove_breakpoint,
        .add_watchpoint = arm7_9_add_watchpoint,
        .add_breakpoint = arm7_9_add_breakpoint,
        .remove_breakpoint = arm7_9_remove_breakpoint,
        .add_watchpoint = arm7_9_add_watchpoint,
@@ -393,9 +397,13 @@ void arm9tdmi_change_to_arm(target_t *target, u32 *r0, u32 *pc)
        /* nothing fetched, STR r0, [r0] in Memory */
        arm9tdmi_clock_out(jtag_info, ARMV4_5_T_NOP, 0, pc, 0);
 
        /* nothing fetched, STR r0, [r0] in Memory */
        arm9tdmi_clock_out(jtag_info, ARMV4_5_T_NOP, 0, pc, 0);
 
-       /* fetch MOV */
-       arm9tdmi_clock_out(jtag_info, ARMV4_5_T_MOV_IM(0, 0x0), 0, NULL, 0);
+       /* use pc-relative LDR to clear r0[1:0] (for switch to ARM mode) */
+       arm9tdmi_clock_out(jtag_info, ARMV4_5_T_LDR_PCREL(0), 0, NULL, 0);
+       /* LDR in Decode */
+       arm9tdmi_clock_out(jtag_info, ARMV4_5_T_NOP, 0, NULL, 0);
+       /* LDR in Execute */
        arm9tdmi_clock_out(jtag_info, ARMV4_5_T_NOP, 0, NULL, 0);
        arm9tdmi_clock_out(jtag_info, ARMV4_5_T_NOP, 0, NULL, 0);
+       /* LDR in Memory (to account for interlock) */
        arm9tdmi_clock_out(jtag_info, ARMV4_5_T_NOP, 0, NULL, 0);
 
        /* fetch BX */
        arm9tdmi_clock_out(jtag_info, ARMV4_5_T_NOP, 0, NULL, 0);
 
        /* fetch BX */
@@ -716,7 +724,7 @@ void arm9tdmi_branch_resume(target_t *target)
 
 void arm9tdmi_branch_resume_thumb(target_t *target)
 {
 
 void arm9tdmi_branch_resume_thumb(target_t *target)
 {
-       DEBUG("");
+       DEBUG("-");
        
        /* get pointers to arch-specific information */
        armv4_5_common_t *armv4_5 = target->arch_info;
        
        /* get pointers to arch-specific information */
        armv4_5_common_t *armv4_5 = target->arch_info;
@@ -754,10 +762,8 @@ void arm9tdmi_branch_resume_thumb(target_t *target)
        /* target is now in Thumb state */
        embeddedice_read_reg(dbg_stat);
 
        /* target is now in Thumb state */
        embeddedice_read_reg(dbg_stat);
 
-       /* clean r0 bits to avoid alignment problems */
-       arm9tdmi_clock_out(jtag_info, ARMV4_5_T_MOV_IM(0, 0x0), 0, NULL, 0);
        /* load r0 value, MOV_IM in Decode*/
        /* load r0 value, MOV_IM in Decode*/
-       arm9tdmi_clock_out(jtag_info, ARMV4_5_T_LDR(0, 0), 0, NULL, 0);
+       arm9tdmi_clock_out(jtag_info, ARMV4_5_T_LDR_PCREL(0), 0, NULL, 0);
        /* fetch NOP, LDR in Decode, MOV_IM in Execute */
        arm9tdmi_clock_out(jtag_info, ARMV4_5_T_NOP, 0, NULL, 0);
        /* fetch NOP, LDR in Execute */
        /* fetch NOP, LDR in Decode, MOV_IM in Execute */
        arm9tdmi_clock_out(jtag_info, ARMV4_5_T_NOP, 0, NULL, 0);
        /* fetch NOP, LDR in Execute */
@@ -772,7 +778,7 @@ void arm9tdmi_branch_resume_thumb(target_t *target)
 
        embeddedice_read_reg(dbg_stat);
        
 
        embeddedice_read_reg(dbg_stat);
        
-       arm9tdmi_clock_out(jtag_info, ARMV4_5_T_B(0x7f6), 0, NULL, 1);
+       arm9tdmi_clock_out(jtag_info, ARMV4_5_T_B(0x7f7), 0, NULL, 1);
        arm9tdmi_clock_out(jtag_info, ARMV4_5_T_NOP, 0, NULL, 0);
 
 }
        arm9tdmi_clock_out(jtag_info, ARMV4_5_T_NOP, 0, NULL, 0);
 
 }
@@ -782,9 +788,8 @@ void arm9tdmi_enable_single_step(target_t *target)
        /* get pointers to arch-specific information */
        armv4_5_common_t *armv4_5 = target->arch_info;
        arm7_9_common_t *arm7_9 = armv4_5->arch_info;
        /* get pointers to arch-specific information */
        armv4_5_common_t *armv4_5 = target->arch_info;
        arm7_9_common_t *arm7_9 = armv4_5->arch_info;
-       arm9tdmi_common_t *arm9 = arm7_9->arch_info;
        
        
-       if (arm9->has_single_step)
+       if (arm7_9->has_single_step)
        {
                buf_set_u32(arm7_9->eice_cache->reg_list[EICE_DBG_CTRL].value, 3, 1, 1);
                embeddedice_store_reg(&arm7_9->eice_cache->reg_list[EICE_DBG_CTRL]);
        {
                buf_set_u32(arm7_9->eice_cache->reg_list[EICE_DBG_CTRL].value, 3, 1, 1);
                embeddedice_store_reg(&arm7_9->eice_cache->reg_list[EICE_DBG_CTRL]);
@@ -800,9 +805,8 @@ void arm9tdmi_disable_single_step(target_t *target)
        /* get pointers to arch-specific information */
        armv4_5_common_t *armv4_5 = target->arch_info;
        arm7_9_common_t *arm7_9 = armv4_5->arch_info;
        /* get pointers to arch-specific information */
        armv4_5_common_t *armv4_5 = target->arch_info;
        arm7_9_common_t *arm7_9 = armv4_5->arch_info;
-       arm9tdmi_common_t *arm9 = arm7_9->arch_info;
        
        
-       if (arm9->has_single_step)
+       if (arm7_9->has_single_step)
        {
                buf_set_u32(arm7_9->eice_cache->reg_list[EICE_DBG_CTRL].value, 3, 1, 0);
                embeddedice_store_reg(&arm7_9->eice_cache->reg_list[EICE_DBG_CTRL]);
        {
                buf_set_u32(arm7_9->eice_cache->reg_list[EICE_DBG_CTRL].value, 3, 1, 0);
                embeddedice_store_reg(&arm7_9->eice_cache->reg_list[EICE_DBG_CTRL]);
@@ -820,34 +824,25 @@ void arm9tdmi_build_reg_cache(target_t *target)
        armv4_5_common_t *armv4_5 = target->arch_info;
        arm7_9_common_t *arm7_9 = armv4_5->arch_info;
        arm_jtag_t *jtag_info = &arm7_9->jtag_info;
        armv4_5_common_t *armv4_5 = target->arch_info;
        arm7_9_common_t *arm7_9 = armv4_5->arch_info;
        arm_jtag_t *jtag_info = &arm7_9->jtag_info;
-       arm9tdmi_common_t *arm9tdmi = arm7_9->arch_info;
-
-       embeddedice_reg_t *vec_catch_arch_info;
 
        (*cache_p) = armv4_5_build_reg_cache(target, armv4_5);
        armv4_5->core_cache = (*cache_p);
        
        /* one extra register (vector catch) */
 
        (*cache_p) = armv4_5_build_reg_cache(target, armv4_5);
        armv4_5->core_cache = (*cache_p);
        
        /* one extra register (vector catch) */
-       (*cache_p)->next = embeddedice_build_reg_cache(target, jtag_info, 1);
+       (*cache_p)->next = embeddedice_build_reg_cache(target, arm7_9);
        arm7_9->eice_cache = (*cache_p)->next;
        arm7_9->eice_cache = (*cache_p)->next;
-       
-       if (arm9tdmi->has_monitor_mode)
-               (*cache_p)->next->reg_list[EICE_DBG_CTRL].size = 6;
-       else
-               (*cache_p)->next->reg_list[EICE_DBG_CTRL].size = 4;
-       
-       (*cache_p)->next->reg_list[EICE_DBG_STAT].size = 5;
 
 
-       (*cache_p)->next->reg_list[EICE_VEC_CATCH].name = "vector catch";
-       (*cache_p)->next->reg_list[EICE_VEC_CATCH].dirty = 0;
-       (*cache_p)->next->reg_list[EICE_VEC_CATCH].valid = 0;
-       (*cache_p)->next->reg_list[EICE_VEC_CATCH].bitfield_desc = NULL;
-       (*cache_p)->next->reg_list[EICE_VEC_CATCH].num_bitfields = 0;
-       (*cache_p)->next->reg_list[EICE_VEC_CATCH].size = 8;
-       (*cache_p)->next->reg_list[EICE_VEC_CATCH].value = calloc(1, 4);
-       vec_catch_arch_info = (*cache_p)->next->reg_list[EICE_VEC_CATCH].arch_info;
-       vec_catch_arch_info->addr = 0x2;
+       if (arm7_9->has_etm)
+       {
+               (*cache_p)->next->next = etm_build_reg_cache(target, jtag_info, 0);
+               arm7_9->etm_cache = (*cache_p)->next->next;
+       }
        
        
+       if (arm7_9->etb)
+       {
+               (*cache_p)->next->next->next = etb_build_reg_cache(arm7_9->etb);
+               arm7_9->etb->reg_cache = (*cache_p)->next->next->next;
+       }
 }
 
 int arm9tdmi_init_target(struct command_context_s *cmd_ctx, struct target_s *target)
 }
 
 int arm9tdmi_init_target(struct command_context_s *cmd_ctx, struct target_s *target)
@@ -919,27 +914,24 @@ int arm9tdmi_init_arch_info(target_t *target, arm9tdmi_common_t *arm9tdmi, int c
        arm7_9->arch_info = arm9tdmi;
        
        arm9tdmi->common_magic = ARM9TDMI_COMMON_MAGIC;
        arm7_9->arch_info = arm9tdmi;
        
        arm9tdmi->common_magic = ARM9TDMI_COMMON_MAGIC;
-       arm9tdmi->has_monitor_mode = 0;
-       arm9tdmi->has_single_step = 0;
        arm9tdmi->arch_info = NULL;
 
        if (variant)
        {
        arm9tdmi->arch_info = NULL;
 
        if (variant)
        {
-               if (strcmp(variant, "arm920t") == 0)
-                       arm9tdmi->has_single_step = 1;
-               else if (strcmp(variant, "arm922t") == 0)
-                       arm9tdmi->has_single_step = 1;
-               else if (strcmp(variant, "arm940t") == 0)
-                       arm9tdmi->has_single_step = 1;
                arm9tdmi->variant = strdup(variant);
        }
        else
                arm9tdmi->variant = strdup(variant);
        }
        else
+       {
                arm9tdmi->variant = strdup("");
                arm9tdmi->variant = strdup("");
+       }
        
        arm7_9_init_arch_info(target, arm7_9);
 
        /* override use of DBGRQ, this is safe on ARM9TDMI */
        arm7_9->use_dbgrq = 1;
        
        arm7_9_init_arch_info(target, arm7_9);
 
        /* override use of DBGRQ, this is safe on ARM9TDMI */
        arm7_9->use_dbgrq = 1;
+
+       /* all ARM9s have the vector catch register */
+       arm7_9->has_vector_catch = 1;
        
        return ERROR_OK;
 }
        
        return ERROR_OK;
 }
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