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fix jtag_add_callback() args. The first argument is nothing special, it's just anothe...
[openocd.git] / src / target / arm926ejs.c
diff --git a/src/target/arm926ejs.c b/src/target/arm926ejs.c
index c959f1351386ee25216bfd57430c690a14f48314..e48b1bdf0fa238a2875d2cd2cd851113a375a363 100644 (file)
--- a/src/target/arm926ejs.c
+++ b/src/target/arm926ejs.c
@@ -22,20 +22,15 @@
 #endif
 
 #include "arm926ejs.h"
-#include "jtag.h"
-#include "log.h"
 #include "time_support.h"
+#include "target_type.h"
 
-#include <stdlib.h>
-#include <string.h>
 
 #if 0
 #define _DEBUG_INSTRUCTION_EXECUTION_
 #endif
 
 /* cli handling */
-int arm926ejs_register_commands(struct command_context_s *cmd_ctx);
-
 int arm926ejs_handle_cp15_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc);
 int arm926ejs_handle_cp15i_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc);
 int arm926ejs_handle_virt2phys_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc);
@@ -50,11 +45,9 @@ int arm926ejs_handle_read_mmu_command(struct command_context_s *cmd_ctx, char *c
 int arm926ejs_target_create(struct target_s *target, Jim_Interp *interp);
 int arm926ejs_init_target(struct command_context_s *cmd_ctx, struct target_s *target);
 int arm926ejs_quit(void);
-int arm926ejs_arch_state(struct target_s *target);
-int arm926ejs_read_memory(struct target_s *target, u32 address, u32 size, u32 count, u8 *buffer);
-int arm926ejs_write_memory(struct target_s *target, u32 address, u32 size, u32 count, u8 *buffer);
-int arm926ejs_soft_reset_halt(struct target_s *target);
-static int arm926ejs_virt2phys(struct target_s *target, u32 virtual, u32 *physical);
+int arm926ejs_read_memory(struct target_s *target, uint32_t address, uint32_t size, uint32_t count, uint8_t *buffer);
+
+static int arm926ejs_virt2phys(struct target_s *target, uint32_t virtual, uint32_t *physical);
 static int arm926ejs_mmu(struct target_s *target, int *enabled);
 
 target_type_t arm926ejs_target =
@@ -98,12 +91,15 @@ target_type_t arm926ejs_target =
        .mmu = arm926ejs_mmu
 };
 
-
-int arm926ejs_catch_broken_irscan(u8 *captured, void *priv, scan_field_t *field)
+int arm926ejs_catch_broken_irscan(uint8_t *captured, void *priv, scan_field_t *field)
 {
+       /* FIX!!!! this code should be reenabled. For now it does not check
+        * the queue...*/
+       return 0;
+#if 0
        /* The ARM926EJ-S' instruction register is 4 bits wide */
-       u8 t = *captured & 0xf;
-       u8 t2 = *field->in_check_value & 0xf;
+       uint8_t t = *captured & 0xf;
+       uint8_t t2 = *field->in_check_value & 0xf;
        if (t == t2)
        {
                return ERROR_OK;
@@ -114,26 +110,27 @@ int arm926ejs_catch_broken_irscan(u8 *captured, void *priv, scan_field_t *field)
                return ERROR_OK;
        }
        return ERROR_JTAG_QUEUE_FAILED;;
+#endif
 }
 
 #define ARM926EJS_CP15_ADDR(opcode_1, opcode_2, CRn, CRm) ((opcode_1 << 11) | (opcode_2 << 8) | (CRn << 4) | (CRm << 0))
 
-int arm926ejs_cp15_read(target_t *target, u32 op1, u32 op2, u32 CRn, u32 CRm, u32 *value)
+int arm926ejs_cp15_read(target_t *target, uint32_t op1, uint32_t op2, uint32_t CRn, uint32_t CRm, uint32_t *value)
 {
        int retval = ERROR_OK;
        armv4_5_common_t *armv4_5 = target->arch_info;
        arm7_9_common_t *arm7_9 = armv4_5->arch_info;
        arm_jtag_t *jtag_info = &arm7_9->jtag_info;
-       u32 address = ARM926EJS_CP15_ADDR(op1, op2, CRn, CRm);
+       uint32_t address = ARM926EJS_CP15_ADDR(op1, op2, CRn, CRm);
        scan_field_t fields[4];
-       u8 address_buf[2];
-       u8 nr_w_buf = 0;
-       u8 access = 1;
+       uint8_t address_buf[2];
+       uint8_t nr_w_buf = 0;
+       uint8_t access = 1;
 
        buf_set_u32(address_buf, 0, 14, address);
 
-       jtag_add_end_state(TAP_IDLE);
-       if((retval = arm_jtag_scann(jtag_info, 0xf)) != ERROR_OK)
+       jtag_set_end_state(TAP_IDLE);
+       if ((retval = arm_jtag_scann(jtag_info, 0xf)) != ERROR_OK)
        {
                return retval;
        }
@@ -142,47 +139,25 @@ int arm926ejs_cp15_read(target_t *target, u32 op1, u32 op2, u32 CRn, u32 CRm, u3
        fields[0].tap = jtag_info->tap;
        fields[0].num_bits = 32;
        fields[0].out_value = NULL;
-       fields[0].out_mask = NULL;
-       fields[0].in_value = NULL;
-       fields[0].in_check_value = NULL;
-       fields[0].in_check_mask = NULL;
-       fields[0].in_handler = NULL;
-       fields[0].in_handler_priv = NULL;
+       fields[0].in_value = (uint8_t *)value;
+
 
        fields[1].tap = jtag_info->tap;
        fields[1].num_bits = 1;
        fields[1].out_value = &access;
-       fields[1].out_mask = NULL;
        fields[1].in_value = &access;
-       fields[1].in_check_value = NULL;
-       fields[1].in_check_mask = NULL;
-       fields[1].in_handler = NULL;
-       fields[1].in_handler_priv = NULL;
 
        fields[2].tap = jtag_info->tap;
        fields[2].num_bits = 14;
        fields[2].out_value = address_buf;
-       fields[2].out_mask = NULL;
        fields[2].in_value = NULL;
-       fields[2].in_check_value = NULL;
-       fields[2].in_check_mask = NULL;
-       fields[2].in_handler = NULL;
-       fields[2].in_handler_priv = NULL;
 
        fields[3].tap = jtag_info->tap;
        fields[3].num_bits = 1;
        fields[3].out_value = &nr_w_buf;
-       fields[3].out_mask = NULL;
        fields[3].in_value = NULL;
-       fields[3].in_check_value = NULL;
-       fields[3].in_check_mask = NULL;
-       fields[3].in_handler = NULL;
-       fields[3].in_handler_priv = NULL;
-
-       jtag_add_dr_scan(4, fields, -1);
 
-       fields[0].in_handler_priv = value;
-       fields[0].in_handler = arm_jtag_buf_to_u32;
+       jtag_add_dr_scan(4, fields, jtag_get_end_state());
 
        /*TODO: add timeout*/
        do
@@ -190,8 +165,11 @@ int arm926ejs_cp15_read(target_t *target, u32 op1, u32 op2, u32 CRn, u32 CRm, u3
                /* rescan with NOP, to wait for the access to complete */
                access = 0;
                nr_w_buf = 0;
-               jtag_add_dr_scan(4, fields, -1);
-               if((retval = jtag_execute_queue()) != ERROR_OK)
+               jtag_add_dr_scan(4, fields, jtag_get_end_state());
+
+               jtag_add_callback(arm_le_to_h_u32, (jtag_callback_data_t)value);
+
+               if ((retval = jtag_execute_queue()) != ERROR_OK)
                {
                        return retval;
                }
@@ -206,24 +184,24 @@ int arm926ejs_cp15_read(target_t *target, u32 op1, u32 op2, u32 CRn, u32 CRm, u3
        return ERROR_OK;
 }
 
-int arm926ejs_cp15_write(target_t *target, u32 op1, u32 op2, u32 CRn, u32 CRm, u32 value)
+int arm926ejs_cp15_write(target_t *target, uint32_t op1, uint32_t op2, uint32_t CRn, uint32_t CRm, uint32_t value)
 {
        int retval = ERROR_OK;
        armv4_5_common_t *armv4_5 = target->arch_info;
        arm7_9_common_t *arm7_9 = armv4_5->arch_info;
        arm_jtag_t *jtag_info = &arm7_9->jtag_info;
-       u32 address = ARM926EJS_CP15_ADDR(op1, op2, CRn, CRm);
+       uint32_t address = ARM926EJS_CP15_ADDR(op1, op2, CRn, CRm);
        scan_field_t fields[4];
-       u8 value_buf[4];
-       u8 address_buf[2];
-       u8 nr_w_buf = 1;
-       u8 access = 1;
+       uint8_t value_buf[4];
+       uint8_t address_buf[2];
+       uint8_t nr_w_buf = 1;
+       uint8_t access = 1;
 
        buf_set_u32(address_buf, 0, 14, address);
        buf_set_u32(value_buf, 0, 32, value);
 
-       jtag_add_end_state(TAP_IDLE);
-       if((retval = arm_jtag_scann(jtag_info, 0xf)) != ERROR_OK)
+       jtag_set_end_state(TAP_IDLE);
+       if ((retval = arm_jtag_scann(jtag_info, 0xf)) != ERROR_OK)
        {
                return retval;
        }
@@ -232,52 +210,32 @@ int arm926ejs_cp15_write(target_t *target, u32 op1, u32 op2, u32 CRn, u32 CRm, u
        fields[0].tap = jtag_info->tap;
        fields[0].num_bits = 32;
        fields[0].out_value = value_buf;
-       fields[0].out_mask = NULL;
        fields[0].in_value = NULL;
-       fields[0].in_check_value = NULL;
-       fields[0].in_check_mask = NULL;
-       fields[0].in_handler = NULL;
-       fields[0].in_handler_priv = NULL;
 
        fields[1].tap = jtag_info->tap;
        fields[1].num_bits = 1;
        fields[1].out_value = &access;
-       fields[1].out_mask = NULL;
        fields[1].in_value = &access;
-       fields[1].in_check_value = NULL;
-       fields[1].in_check_mask = NULL;
-       fields[1].in_handler = NULL;
-       fields[1].in_handler_priv = NULL;
 
        fields[2].tap = jtag_info->tap;
        fields[2].num_bits = 14;
        fields[2].out_value = address_buf;
-       fields[2].out_mask = NULL;
        fields[2].in_value = NULL;
-       fields[2].in_check_value = NULL;
-       fields[2].in_check_mask = NULL;
-       fields[2].in_handler = NULL;
-       fields[2].in_handler_priv = NULL;
 
        fields[3].tap = jtag_info->tap;
        fields[3].num_bits = 1;
        fields[3].out_value = &nr_w_buf;
-       fields[3].out_mask = NULL;
        fields[3].in_value = NULL;
-       fields[3].in_check_value = NULL;
-       fields[3].in_check_mask = NULL;
-       fields[3].in_handler = NULL;
-       fields[3].in_handler_priv = NULL;
 
-       jtag_add_dr_scan(4, fields, -1);
+       jtag_add_dr_scan(4, fields, jtag_get_end_state());
        /*TODO: add timeout*/
        do
        {
                /* rescan with NOP, to wait for the access to complete */
                access = 0;
                nr_w_buf = 0;
-               jtag_add_dr_scan(4, fields, -1);
-               if((retval = jtag_execute_queue()) != ERROR_OK)
+               jtag_add_dr_scan(4, fields, jtag_get_end_state());
+               if ((retval = jtag_execute_queue()) != ERROR_OK)
                {
                        return retval;
                }
@@ -375,14 +333,14 @@ int arm926ejs_examine_debug_reason(target_t *target)
        return retval;
 }
 
-u32 arm926ejs_get_ttb(target_t *target)
+uint32_t arm926ejs_get_ttb(target_t *target)
 {
        armv4_5_common_t *armv4_5 = target->arch_info;
        arm7_9_common_t *arm7_9 = armv4_5->arch_info;
        arm9tdmi_common_t *arm9tdmi = arm7_9->arch_info;
        arm926ejs_common_t *arm926ejs = arm9tdmi->arch_info;
        int retval;
-       u32 ttb = 0x0;
+       uint32_t ttb = 0x0;
 
        if ((retval = arm926ejs->read_cp15(target, 0, 0, 2, 0, &ttb)) != ERROR_OK)
                return retval;
@@ -396,7 +354,7 @@ void arm926ejs_disable_mmu_caches(target_t *target, int mmu, int d_u_cache, int
        arm7_9_common_t *arm7_9 = armv4_5->arch_info;
        arm9tdmi_common_t *arm9tdmi = arm7_9->arch_info;
        arm926ejs_common_t *arm926ejs = arm9tdmi->arch_info;
-       u32 cp15_control;
+       uint32_t cp15_control;
 
        /* read cp15 control register */
        arm926ejs->read_cp15(target, 0, 0, 1, 0, &cp15_control);
@@ -412,7 +370,7 @@ void arm926ejs_disable_mmu_caches(target_t *target, int mmu, int d_u_cache, int
 
        if (d_u_cache)
        {
-               u32 debug_override;
+               uint32_t debug_override;
                /* read-modify-write CP15 debug override register
                 * to enable "test and clean all" */
                arm926ejs->read_cp15(target, 0, 0, 15, 0, &debug_override);
@@ -447,7 +405,7 @@ void arm926ejs_enable_mmu_caches(target_t *target, int mmu, int d_u_cache, int i
        arm7_9_common_t *arm7_9 = armv4_5->arch_info;
        arm9tdmi_common_t *arm9tdmi = arm7_9->arch_info;
        arm926ejs_common_t *arm926ejs = arm9tdmi->arch_info;
-       u32 cp15_control;
+       uint32_t cp15_control;
 
        /* read cp15 control register */
        arm926ejs->read_cp15(target, 0, 0, 1, 0, &cp15_control);
@@ -479,7 +437,7 @@ void arm926ejs_post_debug_entry(target_t *target)
 
        if (arm926ejs->armv4_5_mmu.armv4_5_cache.ctype == -1)
        {
-               u32 cache_type_reg;
+               uint32_t cache_type_reg;
                /* identify caches */
                arm926ejs->read_cp15(target, 0, 1, 0, 0, &cache_type_reg);
                jtag_execute_queue();
@@ -498,8 +456,7 @@ void arm926ejs_post_debug_entry(target_t *target)
        LOG_DEBUG("D FSR: 0x%8.8x, D FAR: 0x%8.8x, I FSR: 0x%8.8x",
                arm926ejs->d_fsr, arm926ejs->d_far, arm926ejs->i_fsr);
 
-
-       u32 cache_dbg_ctrl;
+       uint32_t cache_dbg_ctrl;
 
        /* read-modify-write CP15 cache debug control register
         * to disable I/D-cache linefills and force WT */
@@ -520,7 +477,7 @@ void arm926ejs_pre_restore_context(target_t *target)
        arm926ejs->write_cp15(target, 0, 1, 5, 0, arm926ejs->i_fsr);
        arm926ejs->write_cp15(target, 0, 0, 6, 0, arm926ejs->d_far);
 
-       u32 cache_dbg_ctrl;
+       uint32_t cache_dbg_ctrl;
 
        /* read-modify-write CP15 cache debug control register
         * to reenable I/D-cache linefills and disable WT */
@@ -610,7 +567,7 @@ int arm926ejs_soft_reset_halt(struct target_s *target)
        arm926ejs_common_t *arm926ejs = arm9tdmi->arch_info;
        reg_t *dbg_stat = &arm7_9->eice_cache->reg_list[EICE_DBG_STAT];
 
-       if((retval = target_halt(target)) != ERROR_OK)
+       if ((retval = target_halt(target)) != ERROR_OK)
        {
                return retval;
        }
@@ -622,7 +579,7 @@ int arm926ejs_soft_reset_halt(struct target_s *target)
                if (buf_get_u32(dbg_stat->value, EICE_DBG_STATUS_DBGACK, 1) == 0)
                {
                        embeddedice_read_reg(dbg_stat);
-                       if((retval = jtag_execute_queue()) != ERROR_OK)
+                       if ((retval = jtag_execute_queue()) != ERROR_OK)
                        {
                                return retval;
                        }
@@ -666,10 +623,9 @@ int arm926ejs_soft_reset_halt(struct target_s *target)
        arm926ejs->armv4_5_mmu.armv4_5_cache.i_cache_enabled = 0;
 
        return target_call_event_callbacks(target, TARGET_EVENT_HALTED);
-
 }
 
-int arm926ejs_write_memory(struct target_s *target, u32 address, u32 size, u32 count, u8 *buffer)
+int arm926ejs_write_memory(struct target_s *target, uint32_t address, uint32_t size, uint32_t count, uint8_t *buffer)
 {
        int retval;
        armv4_5_common_t *armv4_5 = target->arch_info;
@@ -705,23 +661,21 @@ int arm926ejs_init_target(struct command_context_s *cmd_ctx, struct target_s *ta
        arm9tdmi_init_target(cmd_ctx, target);
 
        return ERROR_OK;
-
 }
 
 int arm926ejs_quit(void)
 {
-
        return ERROR_OK;
 }
 
-int arm926ejs_init_arch_info(target_t *target, arm926ejs_common_t *arm926ejs, jtag_tap_t *tap, const char *variant)
+int arm926ejs_init_arch_info(target_t *target, arm926ejs_common_t *arm926ejs, jtag_tap_t *tap)
 {
        arm9tdmi_common_t *arm9tdmi = &arm926ejs->arm9tdmi_common;
        arm7_9_common_t *arm7_9 = &arm9tdmi->arm7_9_common;
 
        /* initialize arm9tdmi specific info (including arm7_9 and armv4_5)
         */
-       arm9tdmi_init_arch_info(target, arm9tdmi, tap, variant);
+       arm9tdmi_init_arch_info(target, arm9tdmi, tap);
 
        arm9tdmi->arch_info = arm926ejs;
        arm926ejs->common_magic = ARM926EJS_COMMON_MAGIC;
@@ -755,7 +709,7 @@ int arm926ejs_target_create(struct target_s *target, Jim_Interp *interp)
 {
        arm926ejs_common_t *arm926ejs = calloc(1,sizeof(arm926ejs_common_t));
 
-       arm926ejs_init_arch_info(target, arm926ejs, target->tap, target->variant);
+       arm926ejs_init_arch_info(target, arm926ejs, target->tap);
 
        return ERROR_OK;
 }
@@ -824,13 +778,13 @@ int arm926ejs_handle_cp15_command(struct command_context_s *cmd_ctx, char *cmd,
 
        if (argc == 4)
        {
-               u32 value;
+               uint32_t value;
                if ((retval = arm926ejs->read_cp15(target, opcode_1, opcode_2, CRn, CRm, &value)) != ERROR_OK)
                {
                        command_print(cmd_ctx, "couldn't access register");
                        return ERROR_OK;
                }
-               if((retval = jtag_execute_queue()) != ERROR_OK)
+               if ((retval = jtag_execute_queue()) != ERROR_OK)
                {
                        return retval;
                }
@@ -839,7 +793,7 @@ int arm926ejs_handle_cp15_command(struct command_context_s *cmd_ctx, char *cmd,
        }
        else
        {
-               u32 value = strtoul(args[4], NULL, 0);
+               uint32_t value = strtoul(args[4], NULL, 0);
                if ((retval = arm926ejs->write_cp15(target, opcode_1, opcode_2, CRn, CRm, value)) != ERROR_OK)
                {
                        command_print(cmd_ctx, "couldn't access register");
@@ -945,13 +899,14 @@ int arm926ejs_handle_mw_phys_command(command_context_t *cmd_ctx, char *cmd, char
 
        return armv4_5_mmu_handle_mw_phys_command(cmd_ctx, cmd, args, argc, target, &arm926ejs->armv4_5_mmu);
 }
-static int arm926ejs_virt2phys(struct target_s *target, u32 virtual, u32 *physical)
+
+static int arm926ejs_virt2phys(struct target_s *target, uint32_t virtual, uint32_t *physical)
 {
        int retval;
        int type;
-       u32 cb;
+       uint32_t cb;
        int domain;
-       u32 ap;
+       uint32_t ap;
 
        armv4_5_common_t *armv4_5;
        arm7_9_common_t *arm7_9;
@@ -962,7 +917,7 @@ static int arm926ejs_virt2phys(struct target_s *target, u32 virtual, u32 *physic
        {
                return retval;
        }
-       u32 ret = armv4_5_mmu_translate_va(target, &arm926ejs->armv4_5_mmu, virtual, &type, &cb, &domain, &ap);
+       uint32_t ret = armv4_5_mmu_translate_va(target, &arm926ejs->armv4_5_mmu, virtual, &type, &cb, &domain, &ap);
        if (type == -1)
        {
                return ret;
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