#endif
/* cli handling */
-int arm926ejs_register_commands(struct command_context_s *cmd_ctx);
-
int arm926ejs_handle_cp15_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc);
int arm926ejs_handle_cp15i_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc);
int arm926ejs_handle_virt2phys_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc);
int arm926ejs_target_create(struct target_s *target, Jim_Interp *interp);
int arm926ejs_init_target(struct command_context_s *cmd_ctx, struct target_s *target);
int arm926ejs_quit(void);
-int arm926ejs_arch_state(struct target_s *target);
int arm926ejs_read_memory(struct target_s *target, u32 address, u32 size, u32 count, u8 *buffer);
-int arm926ejs_write_memory(struct target_s *target, u32 address, u32 size, u32 count, u8 *buffer);
-int arm926ejs_soft_reset_halt(struct target_s *target);
+
static int arm926ejs_virt2phys(struct target_s *target, u32 virtual, u32 *physical);
static int arm926ejs_mmu(struct target_s *target, int *enabled);
.mmu = arm926ejs_mmu
};
-
int arm926ejs_catch_broken_irscan(u8 *captured, void *priv, scan_field_t *field)
{
/* The ARM926EJ-S' instruction register is 4 bits wide */
fields[3].in_handler = NULL;
fields[3].in_handler_priv = NULL;
- jtag_add_dr_scan(4, fields, -1);
+ jtag_add_dr_scan(4, fields, TAP_INVALID);
fields[0].in_handler_priv = value;
fields[0].in_handler = arm_jtag_buf_to_u32;
/* rescan with NOP, to wait for the access to complete */
access = 0;
nr_w_buf = 0;
- jtag_add_dr_scan(4, fields, -1);
+ jtag_add_dr_scan(4, fields, TAP_INVALID);
if((retval = jtag_execute_queue()) != ERROR_OK)
{
return retval;
fields[3].in_handler = NULL;
fields[3].in_handler_priv = NULL;
- jtag_add_dr_scan(4, fields, -1);
+ jtag_add_dr_scan(4, fields, TAP_INVALID);
/*TODO: add timeout*/
do
{
/* rescan with NOP, to wait for the access to complete */
access = 0;
nr_w_buf = 0;
- jtag_add_dr_scan(4, fields, -1);
+ jtag_add_dr_scan(4, fields, TAP_INVALID);
if((retval = jtag_execute_queue()) != ERROR_OK)
{
return retval;
LOG_DEBUG("D FSR: 0x%8.8x, D FAR: 0x%8.8x, I FSR: 0x%8.8x",
arm926ejs->d_fsr, arm926ejs->d_far, arm926ejs->i_fsr);
-
u32 cache_dbg_ctrl;
/* read-modify-write CP15 cache debug control register
arm926ejs->armv4_5_mmu.armv4_5_cache.i_cache_enabled = 0;
return target_call_event_callbacks(target, TARGET_EVENT_HALTED);
-
}
int arm926ejs_write_memory(struct target_s *target, u32 address, u32 size, u32 count, u8 *buffer)
arm9tdmi_init_target(cmd_ctx, target);
return ERROR_OK;
-
}
int arm926ejs_quit(void)
{
-
return ERROR_OK;
}
-int arm926ejs_init_arch_info(target_t *target, arm926ejs_common_t *arm926ejs, jtag_tap_t *tap, const char *variant)
+int arm926ejs_init_arch_info(target_t *target, arm926ejs_common_t *arm926ejs, jtag_tap_t *tap)
{
arm9tdmi_common_t *arm9tdmi = &arm926ejs->arm9tdmi_common;
arm7_9_common_t *arm7_9 = &arm9tdmi->arm7_9_common;
/* initialize arm9tdmi specific info (including arm7_9 and armv4_5)
*/
- arm9tdmi_init_arch_info(target, arm9tdmi, tap, variant);
+ arm9tdmi_init_arch_info(target, arm9tdmi, tap);
arm9tdmi->arch_info = arm926ejs;
arm926ejs->common_magic = ARM926EJS_COMMON_MAGIC;
{
arm926ejs_common_t *arm926ejs = calloc(1,sizeof(arm926ejs_common_t));
- arm926ejs_init_arch_info(target, arm926ejs, target->tap, target->variant);
+ arm926ejs_init_arch_info(target, arm926ejs, target->tap);
return ERROR_OK;
}
return armv4_5_mmu_handle_mw_phys_command(cmd_ctx, cmd, args, argc, target, &arm926ejs->armv4_5_mmu);
}
+
static int arm926ejs_virt2phys(struct target_s *target, u32 virtual, u32 *physical)
{
int retval;