- fixes issue with reset and arm926ejs core. Thanks Øyvind Harboe

[openocd.git] / src / target / arm926ejs.c

diff --git a/src/target/arm926ejs.c b/src/target/arm926ejs.c
index 3931e89871af8d0e3b57ae3cd7d88286118bf5eb..8a609b0762504e4711fa190d95a186b966ac25ed 100644 (file)
--- a/src/target/arm926ejs.c
+++ b/src/target/arm926ejs.c
@@ -28,7 +28,7 @@
 #include <stdlib.h>
 #include <string.h>
 
-#if 0
+#if 1
 #define _DEBUG_INSTRUCTION_EXECUTION_
 #endif
 
@@ -63,6 +63,8 @@ target_type_t arm926ejs_target =
        .poll = arm7_9_poll,
        .arch_state = arm926ejs_arch_state,
 
+       .target_request_data = arm7_9_target_request_data,
+
        .halt = arm7_9_halt,
        .resume = arm7_9_resume,
        .step = arm7_9_step,
@@ -77,7 +79,8 @@ target_type_t arm926ejs_target =
        .read_memory = arm7_9_read_memory,
        .write_memory = arm926ejs_write_memory,
        .bulk_write_memory = arm7_9_bulk_write_memory,
-
+       .checksum_memory = arm7_9_checksum_memory,
+       
        .run_algorithm = armv4_5_run_algorithm,
 
        .add_breakpoint = arm7_9_add_breakpoint,
@@ -91,6 +94,24 @@ target_type_t arm926ejs_target =
        .quit = arm926ejs_quit
 };
 
+
+int arm926ejs_catch_broken_irscan(u8 *captured, void *priv, scan_field_t *field)
+{
+       /* The ARM926EJ-S' instruction register is 4 bits wide */
+       u8 t = *captured & 0xf;
+       u8 t2 = *field->in_check_value & 0xf;
+       if (t == t2)
+       {
+               return ERROR_OK;
+       }
+       else if ((t == 0x0f) || (t == 0x00))
+       {
+               DEBUG("caught ARM926EJ-S invalid Capture-IR result after CP15 access");
+               return ERROR_OK;
+       }
+       return ERROR_JTAG_QUEUE_FAILED;;
+}
+
 int arm926ejs_read_cp15(target_t *target, u32 address, u32 *value)
 {
        armv4_5_common_t *armv4_5 = target->arch_info;
@@ -105,7 +126,7 @@ int arm926ejs_read_cp15(target_t *target, u32 address, u32 *value)
        
        jtag_add_end_state(TAP_RTI);
        arm_jtag_scann(jtag_info, 0xf);
-       arm_jtag_set_instr(jtag_info, jtag_info->intest_instr);
+       arm_jtag_set_instr(jtag_info, jtag_info->intest_instr, NULL);
 
        fields[0].device = jtag_info->chain_pos;
        fields[0].num_bits = 32;
@@ -147,23 +168,25 @@ int arm926ejs_read_cp15(target_t *target, u32 address, u32 *value)
        fields[3].in_handler = NULL;
        fields[3].in_handler_priv = NULL;
        
-       jtag_add_dr_scan(4, fields, -1);
+       jtag_add_dr_scan(4, fields, -1, NULL);
 
-       /* rescan with NOP, to wait for the access to complete */
-       access = 0;
-       
        fields[0].in_handler_priv = value;
        fields[0].in_handler = arm_jtag_buf_to_u32;
        
        do
        {
-               jtag_add_dr_scan(4, fields, -1);
+               /* rescan with NOP, to wait for the access to complete */
+               access = 0;
+               nr_w_buf = 0;
+               jtag_add_dr_scan(4, fields, -1, NULL);
                jtag_execute_queue();
        } while (buf_get_u32(&access, 0, 1) != 1);
 
 #ifdef _DEBUG_INSTRUCTION_EXECUTION_
        DEBUG("addr: 0x%x value: %8.8x", address, *value);
 #endif
+       
+       arm_jtag_set_instr(jtag_info, 0xc, &arm926ejs_catch_broken_irscan);
 
        return ERROR_OK;
 }
@@ -184,7 +207,7 @@ int arm926ejs_write_cp15(target_t *target, u32 address, u32 value)
        
        jtag_add_end_state(TAP_RTI);
        arm_jtag_scann(jtag_info, 0xf);
-       arm_jtag_set_instr(jtag_info, jtag_info->intest_instr);
+       arm_jtag_set_instr(jtag_info, jtag_info->intest_instr, NULL);
 
        fields[0].device = jtag_info->chain_pos;
        fields[0].num_bits = 32;
@@ -226,14 +249,14 @@ int arm926ejs_write_cp15(target_t *target, u32 address, u32 value)
        fields[3].in_handler = NULL;
        fields[3].in_handler_priv = NULL;
        
-       jtag_add_dr_scan(4, fields, -1);
+       jtag_add_dr_scan(4, fields, -1, NULL);
 
-       /* rescan with NOP, to wait for the access to complete */
-       access = 0;
-       
        do
        {
-               jtag_add_dr_scan(4, fields, -1);
+               /* rescan with NOP, to wait for the access to complete */
+               access = 0;
+               nr_w_buf = 0;
+               jtag_add_dr_scan(4, fields, -1, NULL);
                jtag_execute_queue();
        } while (buf_get_u32(&access, 0, 1) != 1);
 
@@ -241,6 +264,8 @@ int arm926ejs_write_cp15(target_t *target, u32 address, u32 value)
        DEBUG("addr: 0x%x value: %8.8x", address, value);
 #endif
 
+       arm_jtag_set_instr(jtag_info, 0xf, &arm926ejs_catch_broken_irscan);
+
        return ERROR_OK;
 }
 
@@ -395,7 +420,7 @@ void arm926ejs_post_debug_entry(target_t *target)
        arm7_9_common_t *arm7_9 = armv4_5->arch_info;
        arm9tdmi_common_t *arm9tdmi = arm7_9->arch_info;
        arm926ejs_common_t *arm926ejs = arm9tdmi->arch_info;
-       
+
        /* examine cp15 control reg */
        arm926ejs_read_cp15(target, ARM926EJS_CP15_ADDR(0, 0, 1, 0), &arm926ejs->cp15_control_reg);
        jtag_execute_queue();
@@ -430,7 +455,6 @@ void arm926ejs_post_debug_entry(target_t *target)
        arm926ejs_read_cp15(target, ARM926EJS_CP15_ADDR(7, 0, 15, 0), &cache_dbg_ctrl);
        cache_dbg_ctrl |= 0x7;
        arm926ejs_write_cp15(target, ARM926EJS_CP15_ADDR(7, 0, 15, 0), cache_dbg_ctrl);
-
 }
 
 void arm926ejs_pre_restore_context(target_t *target)
@@ -439,7 +463,7 @@ void arm926ejs_pre_restore_context(target_t *target)
        arm7_9_common_t *arm7_9 = armv4_5->arch_info;
        arm9tdmi_common_t *arm9tdmi = arm7_9->arch_info;
        arm926ejs_common_t *arm926ejs = arm9tdmi->arch_info;
-       
+
        /* restore i/d fault status and address register */
        arm926ejs_write_cp15(target, ARM926EJS_CP15_ADDR(0, 0, 5, 0), arm926ejs->d_fsr);
        arm926ejs_write_cp15(target, ARM926EJS_CP15_ADDR(0, 1, 5, 0), arm926ejs->i_fsr);
@@ -450,7 +474,7 @@ void arm926ejs_pre_restore_context(target_t *target)
        /* read-modify-write CP15 cache debug control register 
         * to reenable I/D-cache linefills and disable WT */
        arm926ejs_read_cp15(target, ARM926EJS_CP15_ADDR(7, 0, 15, 0), &cache_dbg_ctrl);
-       cache_dbg_ctrl |= 0x7;
+       cache_dbg_ctrl &= ~0x7;
        arm926ejs_write_cp15(target, ARM926EJS_CP15_ADDR(7, 0, 15, 0), cache_dbg_ctrl);
 }
 
@@ -539,7 +563,7 @@ int arm926ejs_soft_reset_halt(struct target_s *target)
                target->type->halt(target);
        }
        
-       while (buf_get_u32(dbg_stat->value, EICE_DBG_CONTROL_DBGACK, 1) == 0)
+       while (buf_get_u32(dbg_stat->value, EICE_DBG_STATUS_DBGACK, 1) == 0)
        {
                embeddedice_read_reg(dbg_stat);
                jtag_execute_queue();
@@ -641,6 +665,15 @@ int arm926ejs_init_arch_info(target_t *target, arm926ejs_common_t *arm926ejs, in
        
        arm7_9->examine_debug_reason = arm926ejs_examine_debug_reason;
        
+       /* The ARM926EJ-S implements the ARMv5TE architecture which
+        * has the BKPT instruction, so we don't have to use a watchpoint comparator
+        */
+       arm7_9->arm_bkpt = ARMV5_BKPT(0x0);
+       arm7_9->thumb_bkpt = ARMV5_T_BKPT(0x0) & 0xffff;
+       
+       arm7_9->sw_bkpts_use_wp = 0;
+       arm7_9->sw_bkpts_enabled = 1;
+       
        return ERROR_OK;
 }