#include <stdlib.h>
#include <string.h>
-#if 0
+#if 1
#define _DEBUG_INSTRUCTION_EXECUTION_
#endif
int arm926ejs_target_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc, struct target_s *target);
int arm926ejs_init_target(struct command_context_s *cmd_ctx, struct target_s *target);
int arm926ejs_quit();
-int arm926ejs_arch_state(struct target_s *target, char *buf, int buf_size);
+int arm926ejs_arch_state(struct target_s *target);
int arm926ejs_read_memory(struct target_s *target, u32 address, u32 size, u32 count, u8 *buffer);
int arm926ejs_write_memory(struct target_s *target, u32 address, u32 size, u32 count, u8 *buffer);
int arm926ejs_soft_reset_halt(struct target_s *target);
-
-#define ARM926EJS_CP15_ADDR(opcode_1, opcode_2, CRn, CRm) ((opcode_1 << 11) | (opcode_2 << 8) | (CRn << 4) | (CRm << 0))
+static int arm926ejs_virt2phys(struct target_s *target, u32 virtual, u32 *physical);
+static int arm926ejs_mmu(struct target_s *target, int *enabled);
target_type_t arm926ejs_target =
{
.poll = arm7_9_poll,
.arch_state = arm926ejs_arch_state,
+ .target_request_data = arm7_9_target_request_data,
+
.halt = arm7_9_halt,
.resume = arm7_9_resume,
.step = arm7_9_step,
.read_memory = arm7_9_read_memory,
.write_memory = arm926ejs_write_memory,
.bulk_write_memory = arm7_9_bulk_write_memory,
-
+ .checksum_memory = arm7_9_checksum_memory,
+
.run_algorithm = armv4_5_run_algorithm,
.add_breakpoint = arm7_9_add_breakpoint,
.register_commands = arm926ejs_register_commands,
.target_command = arm926ejs_target_command,
.init_target = arm926ejs_init_target,
- .quit = arm926ejs_quit
+ .quit = arm926ejs_quit,
+ .virt2phys = arm926ejs_virt2phys,
+ .mmu = arm926ejs_mmu
};
-int arm926ejs_read_cp15(target_t *target, u32 address, u32 *value)
+
+int arm926ejs_catch_broken_irscan(u8 *captured, void *priv, scan_field_t *field)
+{
+ /* The ARM926EJ-S' instruction register is 4 bits wide */
+ u8 t = *captured & 0xf;
+ u8 t2 = *field->in_check_value & 0xf;
+ if (t == t2)
+ {
+ return ERROR_OK;
+ }
+ else if ((t == 0x0f) || (t == 0x00))
+ {
+ LOG_DEBUG("caught ARM926EJ-S invalid Capture-IR result after CP15 access");
+ return ERROR_OK;
+ }
+ return ERROR_JTAG_QUEUE_FAILED;;
+}
+
+#define ARM926EJS_CP15_ADDR(opcode_1, opcode_2, CRn, CRm) ((opcode_1 << 11) | (opcode_2 << 8) | (CRn << 4) | (CRm << 0))
+
+int arm926ejs_cp15_read(target_t *target, u32 op1, u32 op2, u32 CRn, u32 CRm, u32 *value)
{
armv4_5_common_t *armv4_5 = target->arch_info;
arm7_9_common_t *arm7_9 = armv4_5->arch_info;
arm_jtag_t *jtag_info = &arm7_9->jtag_info;
+ u32 address = ARM926EJS_CP15_ADDR(op1, op2, CRn, CRm);
scan_field_t fields[4];
u8 address_buf[2];
u8 nr_w_buf = 0;
jtag_add_end_state(TAP_RTI);
arm_jtag_scann(jtag_info, 0xf);
- arm_jtag_set_instr(jtag_info, jtag_info->intest_instr);
+ arm_jtag_set_instr(jtag_info, jtag_info->intest_instr, NULL);
fields[0].device = jtag_info->chain_pos;
fields[0].num_bits = 32;
jtag_add_dr_scan(4, fields, -1);
- /* rescan with NOP, to wait for the access to complete */
- access = 0;
-
fields[0].in_handler_priv = value;
fields[0].in_handler = arm_jtag_buf_to_u32;
+ /*TODO: add timeout*/
do
{
+ /* rescan with NOP, to wait for the access to complete */
+ access = 0;
+ nr_w_buf = 0;
jtag_add_dr_scan(4, fields, -1);
jtag_execute_queue();
- } while ((access & 1) != 1);
+ } while (buf_get_u32(&access, 0, 1) != 1);
#ifdef _DEBUG_INSTRUCTION_EXECUTION_
- DEBUG("addr: 0x%x value: %8.8x", address, *value);
+ LOG_DEBUG("addr: 0x%x value: %8.8x", address, *value);
#endif
+
+ arm_jtag_set_instr(jtag_info, 0xc, &arm926ejs_catch_broken_irscan);
return ERROR_OK;
}
-int arm926ejs_write_cp15(target_t *target, u32 address, u32 value)
+int arm926ejs_cp15_write(target_t *target, u32 op1, u32 op2, u32 CRn, u32 CRm, u32 value)
{
armv4_5_common_t *armv4_5 = target->arch_info;
arm7_9_common_t *arm7_9 = armv4_5->arch_info;
arm_jtag_t *jtag_info = &arm7_9->jtag_info;
+ u32 address = ARM926EJS_CP15_ADDR(op1, op2, CRn, CRm);
scan_field_t fields[4];
u8 value_buf[4];
u8 address_buf[2];
jtag_add_end_state(TAP_RTI);
arm_jtag_scann(jtag_info, 0xf);
- arm_jtag_set_instr(jtag_info, jtag_info->intest_instr);
+ arm_jtag_set_instr(jtag_info, jtag_info->intest_instr, NULL);
fields[0].device = jtag_info->chain_pos;
fields[0].num_bits = 32;
fields[3].in_handler_priv = NULL;
jtag_add_dr_scan(4, fields, -1);
-
- /* rescan with NOP, to wait for the access to complete */
- access = 0;
-
+ /*TODO: add timeout*/
do
{
+ /* rescan with NOP, to wait for the access to complete */
+ access = 0;
+ nr_w_buf = 0;
jtag_add_dr_scan(4, fields, -1);
jtag_execute_queue();
- } while (access != 1);
+ } while (buf_get_u32(&access, 0, 1) != 1);
#ifdef _DEBUG_INSTRUCTION_EXECUTION_
- DEBUG("addr: 0x%x value: %8.8x", address, value);
+ LOG_DEBUG("addr: 0x%x value: %8.8x", address, value);
#endif
+ arm_jtag_set_instr(jtag_info, 0xf, &arm926ejs_catch_broken_irscan);
+
return ERROR_OK;
}
switch (debug_reason)
{
case 1:
- DEBUG("breakpoint from EICE unit 0");
+ LOG_DEBUG("breakpoint from EICE unit 0");
target->debug_reason = DBG_REASON_BREAKPOINT;
break;
case 2:
- DEBUG("breakpoint from EICE unit 1");
+ LOG_DEBUG("breakpoint from EICE unit 1");
target->debug_reason = DBG_REASON_BREAKPOINT;
break;
case 3:
- DEBUG("soft breakpoint (BKPT instruction)");
+ LOG_DEBUG("soft breakpoint (BKPT instruction)");
target->debug_reason = DBG_REASON_BREAKPOINT;
break;
case 4:
- DEBUG("vector catch breakpoint");
+ LOG_DEBUG("vector catch breakpoint");
target->debug_reason = DBG_REASON_BREAKPOINT;
break;
case 5:
- DEBUG("external breakpoint");
+ LOG_DEBUG("external breakpoint");
target->debug_reason = DBG_REASON_BREAKPOINT;
break;
case 6:
- DEBUG("watchpoint from EICE unit 0");
+ LOG_DEBUG("watchpoint from EICE unit 0");
target->debug_reason = DBG_REASON_WATCHPOINT;
break;
case 7:
- DEBUG("watchpoint from EICE unit 1");
+ LOG_DEBUG("watchpoint from EICE unit 1");
target->debug_reason = DBG_REASON_WATCHPOINT;
break;
case 8:
- DEBUG("external watchpoint");
+ LOG_DEBUG("external watchpoint");
target->debug_reason = DBG_REASON_WATCHPOINT;
break;
case 9:
- DEBUG("internal debug request");
+ LOG_DEBUG("internal debug request");
target->debug_reason = DBG_REASON_DBGRQ;
break;
case 10:
- DEBUG("external debug request");
+ LOG_DEBUG("external debug request");
target->debug_reason = DBG_REASON_DBGRQ;
break;
case 11:
- ERROR("BUG: debug re-entry from system speed access shouldn't be handled here");
+ LOG_ERROR("BUG: debug re-entry from system speed access shouldn't be handled here");
break;
default:
- ERROR("BUG: unknown debug reason: 0x%x", debug_reason);
+ LOG_ERROR("BUG: unknown debug reason: 0x%x", debug_reason);
target->debug_reason = DBG_REASON_DBGRQ;
+ retval = ERROR_TARGET_FAILURE;
+ break;
}
- return ERROR_OK;
+ return retval;
}
u32 arm926ejs_get_ttb(target_t *target)
{
+ armv4_5_common_t *armv4_5 = target->arch_info;
+ arm7_9_common_t *arm7_9 = armv4_5->arch_info;
+ arm9tdmi_common_t *arm9tdmi = arm7_9->arch_info;
+ arm926ejs_common_t *arm926ejs = arm9tdmi->arch_info;
int retval;
u32 ttb = 0x0;
- if ((retval = arm926ejs_read_cp15(target, ARM926EJS_CP15_ADDR(0, 0, 2, 0), &ttb)) != ERROR_OK)
+ if ((retval = arm926ejs->read_cp15(target, 0, 0, 2, 0, &ttb)) != ERROR_OK)
return retval;
return ttb;
void arm926ejs_disable_mmu_caches(target_t *target, int mmu, int d_u_cache, int i_cache)
{
+ armv4_5_common_t *armv4_5 = target->arch_info;
+ arm7_9_common_t *arm7_9 = armv4_5->arch_info;
+ arm9tdmi_common_t *arm9tdmi = arm7_9->arch_info;
+ arm926ejs_common_t *arm926ejs = arm9tdmi->arch_info;
u32 cp15_control;
/* read cp15 control register */
- arm926ejs_read_cp15(target, ARM926EJS_CP15_ADDR(0, 0, 1, 0), &cp15_control);
+ arm926ejs->read_cp15(target, 0, 0, 1, 0, &cp15_control);
jtag_execute_queue();
if (mmu)
{
/* invalidate TLB */
- arm926ejs_write_cp15(target, ARM926EJS_CP15_ADDR(0, 0, 8, 7), 0x0);
+ arm926ejs->write_cp15(target, 0, 0, 8, 7, 0x0);
cp15_control &= ~0x1U;
}
u32 debug_override;
/* read-modify-write CP15 debug override register
* to enable "test and clean all" */
- arm926ejs_read_cp15(target, ARM926EJS_CP15_ADDR(0, 0, 15, 0), &debug_override);
+ arm926ejs->read_cp15(target, 0, 0, 15, 0, &debug_override);
debug_override |= 0x80000;
- arm926ejs_write_cp15(target, ARM926EJS_CP15_ADDR(0, 0, 15, 0), debug_override);
+ arm926ejs->write_cp15(target, 0, 0, 15, 0, debug_override);
/* clean and invalidate DCache */
- arm926ejs_write_cp15(target, ARM926EJS_CP15_ADDR(0, 0, 7, 5), 0x0);
+ arm926ejs->write_cp15(target, 0, 0, 7, 5, 0x0);
/* write CP15 debug override register
* to disable "test and clean all" */
debug_override &= ~0x80000;
- arm926ejs_write_cp15(target, ARM926EJS_CP15_ADDR(0, 0, 15, 0), debug_override);
+ arm926ejs->write_cp15(target, 0, 0, 15, 0, debug_override);
cp15_control &= ~0x4U;
}
if (i_cache)
{
/* invalidate ICache */
- arm926ejs_write_cp15(target, ARM926EJS_CP15_ADDR(0, 0, 7, 5), 0x0);
+ arm926ejs->write_cp15(target, 0, 0, 7, 5, 0x0);
cp15_control &= ~0x1000U;
}
- arm926ejs_write_cp15(target, ARM926EJS_CP15_ADDR(0, 0, 1, 0), cp15_control);
+ arm926ejs->write_cp15(target, 0, 0, 1, 0, cp15_control);
}
void arm926ejs_enable_mmu_caches(target_t *target, int mmu, int d_u_cache, int i_cache)
{
+ armv4_5_common_t *armv4_5 = target->arch_info;
+ arm7_9_common_t *arm7_9 = armv4_5->arch_info;
+ arm9tdmi_common_t *arm9tdmi = arm7_9->arch_info;
+ arm926ejs_common_t *arm926ejs = arm9tdmi->arch_info;
u32 cp15_control;
/* read cp15 control register */
- arm926ejs_read_cp15(target, ARM926EJS_CP15_ADDR(0, 0, 1, 0), &cp15_control);
+ arm926ejs->read_cp15(target, 0, 0, 1, 0, &cp15_control);
jtag_execute_queue();
if (mmu)
if (i_cache)
cp15_control |= 0x1000U;
- arm926ejs_write_cp15(target, ARM926EJS_CP15_ADDR(0, 0, 1, 0), cp15_control);
+ arm926ejs->write_cp15(target, 0, 0, 1, 0, cp15_control);
}
void arm926ejs_post_debug_entry(target_t *target)
arm7_9_common_t *arm7_9 = armv4_5->arch_info;
arm9tdmi_common_t *arm9tdmi = arm7_9->arch_info;
arm926ejs_common_t *arm926ejs = arm9tdmi->arch_info;
-
+
/* examine cp15 control reg */
- arm926ejs_read_cp15(target, ARM926EJS_CP15_ADDR(0, 0, 1, 0), &arm926ejs->cp15_control_reg);
+ arm926ejs->read_cp15(target, 0, 0, 1, 0, &arm926ejs->cp15_control_reg);
jtag_execute_queue();
- DEBUG("cp15_control_reg: %8.8x", arm926ejs->cp15_control_reg);
+ LOG_DEBUG("cp15_control_reg: %8.8x", arm926ejs->cp15_control_reg);
if (arm926ejs->armv4_5_mmu.armv4_5_cache.ctype == -1)
{
u32 cache_type_reg;
/* identify caches */
- arm926ejs_read_cp15(target, ARM926EJS_CP15_ADDR(0, 1, 0, 0), &cache_type_reg);
+ arm926ejs->read_cp15(target, 0, 1, 0, 0, &cache_type_reg);
jtag_execute_queue();
armv4_5_identify_cache(cache_type_reg, &arm926ejs->armv4_5_mmu.armv4_5_cache);
}
arm926ejs->armv4_5_mmu.armv4_5_cache.i_cache_enabled = (arm926ejs->cp15_control_reg & 0x1000U) ? 1 : 0;
/* save i/d fault status and address register */
- arm926ejs_read_cp15(target, ARM926EJS_CP15_ADDR(0, 0, 5, 0), &arm926ejs->d_fsr);
- arm926ejs_read_cp15(target, ARM926EJS_CP15_ADDR(0, 1, 5, 0), &arm926ejs->i_fsr);
- arm926ejs_read_cp15(target, ARM926EJS_CP15_ADDR(0, 0, 6, 0), &arm926ejs->d_far);
+ arm926ejs->read_cp15(target, 0, 0, 5, 0, &arm926ejs->d_fsr);
+ arm926ejs->read_cp15(target, 0, 1, 5, 0, &arm926ejs->i_fsr);
+ arm926ejs->read_cp15(target, 0, 0, 6, 0, &arm926ejs->d_far);
- DEBUG("D FSR: 0x%8.8x, D FAR: 0x%8.8x, I FSR: 0x%8.8x",
+ LOG_DEBUG("D FSR: 0x%8.8x, D FAR: 0x%8.8x, I FSR: 0x%8.8x",
arm926ejs->d_fsr, arm926ejs->d_far, arm926ejs->i_fsr);
/* read-modify-write CP15 cache debug control register
* to disable I/D-cache linefills and force WT */
- arm926ejs_read_cp15(target, ARM926EJS_CP15_ADDR(7, 0, 15, 0), &cache_dbg_ctrl);
+ arm926ejs->read_cp15(target, 7, 0, 15, 0, &cache_dbg_ctrl);
cache_dbg_ctrl |= 0x7;
- arm926ejs_write_cp15(target, ARM926EJS_CP15_ADDR(7, 0, 15, 0), cache_dbg_ctrl);
-
+ arm926ejs->write_cp15(target, 7, 0, 15, 0, cache_dbg_ctrl);
}
void arm926ejs_pre_restore_context(target_t *target)
arm7_9_common_t *arm7_9 = armv4_5->arch_info;
arm9tdmi_common_t *arm9tdmi = arm7_9->arch_info;
arm926ejs_common_t *arm926ejs = arm9tdmi->arch_info;
-
+
/* restore i/d fault status and address register */
- arm926ejs_write_cp15(target, ARM926EJS_CP15_ADDR(0, 0, 5, 0), arm926ejs->d_fsr);
- arm926ejs_write_cp15(target, ARM926EJS_CP15_ADDR(0, 1, 5, 0), arm926ejs->i_fsr);
- arm926ejs_write_cp15(target, ARM926EJS_CP15_ADDR(0, 0, 6, 0), arm926ejs->d_far);
+ arm926ejs->write_cp15(target, 0, 0, 5, 0, arm926ejs->d_fsr);
+ arm926ejs->write_cp15(target, 0, 1, 5, 0, arm926ejs->i_fsr);
+ arm926ejs->write_cp15(target, 0, 0, 6, 0, arm926ejs->d_far);
u32 cache_dbg_ctrl;
/* read-modify-write CP15 cache debug control register
* to reenable I/D-cache linefills and disable WT */
- arm926ejs_read_cp15(target, ARM926EJS_CP15_ADDR(7, 0, 15, 0), &cache_dbg_ctrl);
- cache_dbg_ctrl |= 0x7;
- arm926ejs_write_cp15(target, ARM926EJS_CP15_ADDR(7, 0, 15, 0), cache_dbg_ctrl);
+ arm926ejs->read_cp15(target, 7, 0, 15, 0, &cache_dbg_ctrl);
+ cache_dbg_ctrl &= ~0x7;
+ arm926ejs->write_cp15(target, 7, 0, 15, 0, cache_dbg_ctrl);
}
int arm926ejs_get_arch_pointers(target_t *target, armv4_5_common_t **armv4_5_p, arm7_9_common_t **arm7_9_p, arm9tdmi_common_t **arm9tdmi_p, arm926ejs_common_t **arm926ejs_p)
return ERROR_OK;
}
-int arm926ejs_arch_state(struct target_s *target, char *buf, int buf_size)
+int arm926ejs_arch_state(struct target_s *target)
{
armv4_5_common_t *armv4_5 = target->arch_info;
arm7_9_common_t *arm7_9 = armv4_5->arch_info;
if (armv4_5->common_magic != ARMV4_5_COMMON_MAGIC)
{
- ERROR("BUG: called for a non-ARMv4/5 target");
+ LOG_ERROR("BUG: called for a non-ARMv4/5 target");
exit(-1);
}
- snprintf(buf, buf_size,
+ LOG_USER(
"target halted in %s state due to %s, current mode: %s\n"
"cpsr: 0x%8.8x pc: 0x%8.8x\n"
"MMU: %s, D-Cache: %s, I-Cache: %s",
arm9tdmi_common_t *arm9tdmi = arm7_9->arch_info;
arm926ejs_common_t *arm926ejs = arm9tdmi->arch_info;
reg_t *dbg_stat = &arm7_9->eice_cache->reg_list[EICE_DBG_STAT];
+ int i;
+
+ target->type->halt(target);
- if (target->state == TARGET_RUNNING)
+ for (i=0; i<10; i++)
{
- target->type->halt(target);
+ if (buf_get_u32(dbg_stat->value, EICE_DBG_STATUS_DBGACK, 1) == 0)
+ {
+ embeddedice_read_reg(dbg_stat);
+ jtag_execute_queue();
+ } else
+ {
+ break;
+ }
+ /* do not eat all CPU, time out after 1 se*/
+ usleep(100*1000);
}
-
- while (buf_get_u32(dbg_stat->value, EICE_DBG_CONTROL_DBGACK, 1) == 0)
+ if (i==10)
{
- embeddedice_read_reg(dbg_stat);
- jtag_execute_queue();
+ LOG_ERROR("Failed to halt CPU after 1 sec");
+ return ERROR_TARGET_TIMEOUT;
}
target->state = TARGET_HALTED;
if (count <= 1)
{
/* invalidate ICache single entry with MVA */
- arm926ejs_write_cp15(target, ARM926EJS_CP15_ADDR(0, 1, 7, 5), address);
+ arm926ejs->write_cp15(target, 0, 1, 7, 5, address);
}
else
{
/* invalidate ICache */
- arm926ejs_write_cp15(target, ARM926EJS_CP15_ADDR(0, 0, 7, 5), address);
+ arm926ejs->write_cp15(target, 0, 0, 7, 5, address);
}
}
arm7_9->post_debug_entry = arm926ejs_post_debug_entry;
arm7_9->pre_restore_context = arm926ejs_pre_restore_context;
+ arm926ejs->read_cp15 = arm926ejs_cp15_read;
+ arm926ejs->write_cp15 = arm926ejs_cp15_write;
arm926ejs->armv4_5_mmu.armv4_5_cache.ctype = -1;
arm926ejs->armv4_5_mmu.get_ttb = arm926ejs_get_ttb;
arm926ejs->armv4_5_mmu.read_memory = arm7_9_read_memory;
arm7_9->examine_debug_reason = arm926ejs_examine_debug_reason;
+ /* The ARM926EJ-S implements the ARMv5TE architecture which
+ * has the BKPT instruction, so we don't have to use a watchpoint comparator
+ */
+ arm7_9->arm_bkpt = ARMV5_BKPT(0x0);
+ arm7_9->thumb_bkpt = ARMV5_T_BKPT(0x0) & 0xffff;
+
+ arm7_9->sw_bkpts_use_wp = 0;
+ arm7_9->sw_bkpts_enabled = 1;
+
return ERROR_OK;
}
int chain_pos;
char *variant = NULL;
arm926ejs_common_t *arm926ejs = malloc(sizeof(arm926ejs_common_t));
+ memset(arm926ejs, 0, sizeof(*arm926ejs));
if (argc < 4)
{
- ERROR("'target arm926ejs' requires at least one additional argument");
+ LOG_ERROR("'target arm926ejs' requires at least one additional argument");
exit(-1);
}
if (argc >= 5)
variant = args[4];
- DEBUG("chain_pos: %i, variant: %s", chain_pos, variant);
+ LOG_DEBUG("chain_pos: %i, variant: %s", chain_pos, variant);
arm926ejs_init_arch_info(target, arm926ejs, chain_pos, variant);
arm7_9_common_t *arm7_9;
arm9tdmi_common_t *arm9tdmi;
arm926ejs_common_t *arm926ejs;
- int opcode_1 = strtoul(args[0], NULL, 0);
- int opcode_2 = strtoul(args[1], NULL, 0);
- int CRn = strtoul(args[2], NULL, 0);
- int CRm = strtoul(args[3], NULL, 0);
+ int opcode_1;
+ int opcode_2;
+ int CRn;
+ int CRm;
+
+ if ((argc < 4) || (argc > 5))
+ {
+ command_print(cmd_ctx, "usage: arm926ejs cp15 <opcode_1> <opcode_2> <CRn> <CRm> [value]");
+ return ERROR_OK;
+ }
+
+ opcode_1 = strtoul(args[0], NULL, 0);
+ opcode_2 = strtoul(args[1], NULL, 0);
+ CRn = strtoul(args[2], NULL, 0);
+ CRm = strtoul(args[3], NULL, 0);
if (arm926ejs_get_arch_pointers(target, &armv4_5, &arm7_9, &arm9tdmi, &arm926ejs) != ERROR_OK)
{
return ERROR_OK;
}
- if ((argc < 4) || (argc > 5))
- {
- command_print(cmd_ctx, "usage: arm926ejs cp15 <opcode_1> <opcode_2> <CRn> <CRm> [value]");
- }
-
if (argc == 4)
{
u32 value;
- if ((retval = arm926ejs_read_cp15(target, ARM926EJS_CP15_ADDR(opcode_1, opcode_2, CRn, CRm), &value)) != ERROR_OK)
+ if ((retval = arm926ejs->read_cp15(target, opcode_1, opcode_2, CRn, CRm, &value)) != ERROR_OK)
{
command_print(cmd_ctx, "couldn't access register");
return ERROR_OK;
else
{
u32 value = strtoul(args[4], NULL, 0);
- if ((retval = arm926ejs_write_cp15(target, ARM926EJS_CP15_ADDR(opcode_1, opcode_2, CRn, CRm), value)) != ERROR_OK)
+ if ((retval = arm926ejs->write_cp15(target, opcode_1, opcode_2, CRn, CRm, value)) != ERROR_OK)
{
command_print(cmd_ctx, "couldn't access register");
return ERROR_OK;
return armv4_5_mmu_handle_mw_phys_command(cmd_ctx, cmd, args, argc, target, &arm926ejs->armv4_5_mmu);
}
+static int arm926ejs_virt2phys(struct target_s *target, u32 virtual, u32 *physical)
+{
+ int retval;
+ int type;
+ u32 cb;
+ int domain;
+ u32 ap;
+
+ armv4_5_common_t *armv4_5;
+ arm7_9_common_t *arm7_9;
+ arm9tdmi_common_t *arm9tdmi;
+ arm926ejs_common_t *arm926ejs;
+ retval= arm926ejs_get_arch_pointers(target, &armv4_5, &arm7_9, &arm9tdmi, &arm926ejs);
+ if (retval != ERROR_OK)
+ {
+ return retval;
+ }
+ u32 ret = armv4_5_mmu_translate_va(target, &arm926ejs->armv4_5_mmu, virtual, &type, &cb, &domain, &ap);
+ if (type == -1)
+ {
+ return ret;
+ }
+ *physical = ret;
+ return ERROR_OK;
+}
+
+static int arm926ejs_mmu(struct target_s *target, int *enabled)
+{
+ armv4_5_common_t *armv4_5 = target->arch_info;
+ arm926ejs_common_t *arm926ejs = armv4_5->arch_info;
+
+ if (target->state != TARGET_HALTED)
+ {
+ LOG_ERROR("Target not halted");
+ return ERROR_TARGET_INVALID;
+ }
+ *enabled = arm926ejs->armv4_5_mmu.mmu_enabled;
+ return ERROR_OK;
+}
Code Review / openocd.git / blobdiff