Code Review / openocd.git / blobdiff
? search:
summary | shortlog | log | commit | commitdiff | review | tree
raw | inline | side by side
cortex_m3: use armv7m's async algorithm implementation
[openocd.git] / src / target / arm920t.c
diff --git a/src/target/arm920t.c b/src/target/arm920t.c
index fe9bba7e9f225587f1cc71f46816ed812b7165c1..f057d7b9b485eb3e101cfb221a354127955d47ab 100644 (file)
--- a/src/target/arm920t.c
+++ b/src/target/arm920t.c
@@ -89,11 +89,16 @@ static int arm920t_read_cp15_physical(struct target *target,
        uint8_t access_type_buf = 1;
        uint8_t reg_addr_buf = reg_addr & 0x3f;
        uint8_t nr_w_buf = 0;
+       int retval;
 
        jtag_info = &arm920t->arm7_9_common.jtag_info;
 
-       arm_jtag_scann(jtag_info, 0xf, TAP_IDLE);
-       arm_jtag_set_instr(jtag_info, jtag_info->intest_instr, NULL, TAP_IDLE);
+       retval = arm_jtag_scann(jtag_info, 0xf, TAP_IDLE);
+       if (retval != ERROR_OK)
+               return retval;
+       retval = arm_jtag_set_instr(jtag_info, jtag_info->intest_instr, NULL, TAP_IDLE);
+       if (retval != ERROR_OK)
+               return retval;
 
        fields[0].num_bits = 1;
        fields[0].out_value = &access_type_buf;
@@ -137,13 +142,18 @@ static int arm920t_write_cp15_physical(struct target *target,
        uint8_t reg_addr_buf = reg_addr & 0x3f;
        uint8_t nr_w_buf = 1;
        uint8_t value_buf[4];
+       int retval;
 
        jtag_info = &arm920t->arm7_9_common.jtag_info;
 
        buf_set_u32(value_buf, 0, 32, value);
 
-       arm_jtag_scann(jtag_info, 0xf, TAP_IDLE);
-       arm_jtag_set_instr(jtag_info, jtag_info->intest_instr, NULL, TAP_IDLE);
+       retval = arm_jtag_scann(jtag_info, 0xf, TAP_IDLE);
+       if (retval != ERROR_OK)
+               return retval;
+       retval = arm_jtag_set_instr(jtag_info, jtag_info->intest_instr, NULL, TAP_IDLE);
+       if (retval != ERROR_OK)
+               return retval;
 
        fields[0].num_bits = 1;
        fields[0].out_value = &access_type_buf;
@@ -191,8 +201,12 @@ static int arm920t_execute_cp15(struct target *target, uint32_t cp15_opcode,
 
        jtag_info = &arm920t->arm7_9_common.jtag_info;
 
-       arm_jtag_scann(jtag_info, 0xf, TAP_IDLE);
-       arm_jtag_set_instr(jtag_info, jtag_info->intest_instr, NULL, TAP_IDLE);
+       retval = arm_jtag_scann(jtag_info, 0xf, TAP_IDLE);
+       if (retval != ERROR_OK)
+               return retval;
+       retval = arm_jtag_set_instr(jtag_info, jtag_info->intest_instr, NULL, TAP_IDLE);
+       if (retval != ERROR_OK)
+               return retval;
 
        buf_set_u32(cp15_opcode_buf, 0, 32, cp15_opcode);
 
@@ -267,7 +281,10 @@ static int arm920t_read_cp15_interpreted(struct target *target,
 #endif
 
        if (!is_arm_mode(armv4_5->core_mode))
+       {
+               LOG_ERROR("not a valid arm core mode - communication failure?");
                return ERROR_FAIL;
+       }
 
        r[0].dirty = 1;
        r[1].dirty = 1;
@@ -309,7 +326,10 @@ int arm920t_write_cp15_interpreted(struct target *target,
 #endif
 
        if (!is_arm_mode(armv4_5->core_mode))
+       {
+               LOG_ERROR("not a valid arm core mode - communication failure?");
                return ERROR_FAIL;
+       }
 
        r[0].dirty = 1;
        r[1].dirty = 1;
@@ -318,7 +338,7 @@ int arm920t_write_cp15_interpreted(struct target *target,
 }
 
 // EXPORTED to FA256
-uint32_t arm920t_get_ttb(struct target *target)
+int arm920t_get_ttb(struct target *target, uint32_t *result)
 {
        int retval;
        uint32_t ttb = 0x0;
@@ -328,18 +348,24 @@ uint32_t arm920t_get_ttb(struct target *target)
                        0xeebf0f51, 0x0, &ttb)) != ERROR_OK)
                return retval;
 
-       return ttb;
+       *result = ttb;
+       return ERROR_OK;
 }
 
 // EXPORTED to FA256
-void arm920t_disable_mmu_caches(struct target *target, int mmu,
+int arm920t_disable_mmu_caches(struct target *target, int mmu,
                int d_u_cache, int i_cache)
 {
        uint32_t cp15_control;
+       int retval;
 
        /* read cp15 control register */
-       arm920t_read_cp15_physical(target, CP15PHYS_CTRL, &cp15_control);
-       jtag_execute_queue();
+       retval = arm920t_read_cp15_physical(target, CP15PHYS_CTRL, &cp15_control);
+       if (retval != ERROR_OK)
+               return retval;
+       retval = jtag_execute_queue();
+       if (retval != ERROR_OK)
+               return retval;
 
        if (mmu)
                cp15_control &= ~0x1U;
@@ -350,18 +376,24 @@ void arm920t_disable_mmu_caches(struct target *target, int mmu,
        if (i_cache)
                cp15_control &= ~0x1000U;
 
-       arm920t_write_cp15_physical(target, CP15PHYS_CTRL, cp15_control);
+       retval = arm920t_write_cp15_physical(target, CP15PHYS_CTRL, cp15_control);
+       return retval;
 }
 
 // EXPORTED to FA256
-void arm920t_enable_mmu_caches(struct target *target, int mmu,
+int arm920t_enable_mmu_caches(struct target *target, int mmu,
                int d_u_cache, int i_cache)
 {
        uint32_t cp15_control;
+       int retval;
 
        /* read cp15 control register */
-       arm920t_read_cp15_physical(target, CP15PHYS_CTRL, &cp15_control);
-       jtag_execute_queue();
+       retval = arm920t_read_cp15_physical(target, CP15PHYS_CTRL, &cp15_control);
+       if (retval != ERROR_OK)
+               return retval;
+       retval = jtag_execute_queue();
+       if (retval != ERROR_OK)
+               return retval;
 
        if (mmu)
                cp15_control |= 0x1U;
@@ -372,28 +404,38 @@ void arm920t_enable_mmu_caches(struct target *target, int mmu,
        if (i_cache)
                cp15_control |= 0x1000U;
 
-       arm920t_write_cp15_physical(target, CP15PHYS_CTRL, cp15_control);
+       retval = arm920t_write_cp15_physical(target, CP15PHYS_CTRL, cp15_control);
+       return retval;
 }
 
 // EXPORTED to FA256
-void arm920t_post_debug_entry(struct target *target)
+int arm920t_post_debug_entry(struct target *target)
 {
        uint32_t cp15c15;
        struct arm920t_common *arm920t = target_to_arm920(target);
+       int retval;
 
        /* examine cp15 control reg */
-       arm920t_read_cp15_physical(target,
+       retval = arm920t_read_cp15_physical(target,
                        CP15PHYS_CTRL, &arm920t->cp15_control_reg);
-       jtag_execute_queue();
+       if (retval != ERROR_OK)
+               return retval;
+       retval = jtag_execute_queue();
+       if (retval != ERROR_OK)
+               return retval;
        LOG_DEBUG("cp15_control_reg: %8.8" PRIx32, arm920t->cp15_control_reg);
 
        if (arm920t->armv4_5_mmu.armv4_5_cache.ctype == -1)
        {
                uint32_t cache_type_reg;
                /* identify caches */
-               arm920t_read_cp15_physical(target,
+               retval = arm920t_read_cp15_physical(target,
                                CP15PHYS_CACHETYPE, &cache_type_reg);
-               jtag_execute_queue();
+               if (retval != ERROR_OK)
+                       return retval;
+               retval = jtag_execute_queue();
+               if (retval != ERROR_OK)
+                       return retval;
                armv4_5_identify_cache(cache_type_reg,
                                &arm920t->armv4_5_mmu.armv4_5_cache);
        }
@@ -407,10 +449,18 @@ void arm920t_post_debug_entry(struct target *target)
 
        /* save i/d fault status and address register */
                        /* FIXME use opcode macros */
-       arm920t_read_cp15_interpreted(target, 0xee150f10, 0x0, &arm920t->d_fsr);
-       arm920t_read_cp15_interpreted(target, 0xee150f30, 0x0, &arm920t->i_fsr);
-       arm920t_read_cp15_interpreted(target, 0xee160f10, 0x0, &arm920t->d_far);
-       arm920t_read_cp15_interpreted(target, 0xee160f30, 0x0, &arm920t->i_far);
+       retval = arm920t_read_cp15_interpreted(target, 0xee150f10, 0x0, &arm920t->d_fsr);
+       if (retval != ERROR_OK)
+               return retval;
+       retval = arm920t_read_cp15_interpreted(target, 0xee150f30, 0x0, &arm920t->i_fsr);
+       if (retval != ERROR_OK)
+               return retval;
+       retval = arm920t_read_cp15_interpreted(target, 0xee160f10, 0x0, &arm920t->d_far);
+       if (retval != ERROR_OK)
+               return retval;
+       retval = arm920t_read_cp15_interpreted(target, 0xee160f30, 0x0, &arm920t->i_far);
+       if (retval != ERROR_OK)
+               return retval;
 
        LOG_DEBUG("D FSR: 0x%8.8" PRIx32 ", D FAR: 0x%8.8" PRIx32
                ", I FSR: 0x%8.8" PRIx32 ", I FAR: 0x%8.8" PRIx32,
@@ -420,13 +470,20 @@ void arm920t_post_debug_entry(struct target *target)
        {
                /* read-modify-write CP15 test state register
                 * to disable I/D-cache linefills */
-               arm920t_read_cp15_physical(target,
+               retval = arm920t_read_cp15_physical(target,
                                CP15PHYS_TESTSTATE, &cp15c15);
-               jtag_execute_queue();
+               if (retval != ERROR_OK)
+                       return retval;
+               retval = jtag_execute_queue();
+               if (retval != ERROR_OK)
+                       return retval;
                cp15c15 |= 0x600;
-               arm920t_write_cp15_physical(target,
+               retval = arm920t_write_cp15_physical(target,
                                CP15PHYS_TESTSTATE, cp15c15);
+               if (retval != ERROR_OK)
+                       return retval;
        }
+       return ERROR_OK;
 }
 
 // EXPORTED to FA256
@@ -476,7 +533,6 @@ int arm920t_arch_state(struct target *target)
        };
 
        struct arm920t_common *arm920t = target_to_arm920(target);
-       struct arm *armv4_5;
 
        if (arm920t->common_magic != ARM920T_COMMON_MAGIC)
        {
@@ -484,8 +540,6 @@ int arm920t_arch_state(struct target *target)
                return ERROR_TARGET_INVALID;
        }
 
-       armv4_5 = &arm920t->arm7_9_common.armv4_5_common;
-
        arm_arch_state(target);
        LOG_USER("MMU: %s, D-Cache: %s, I-Cache: %s",
                 state[arm920t->armv4_5_mmu.mmu_enabled],
@@ -545,7 +599,7 @@ static int arm920t_read_phys_memory(struct target *target,
 
 static int arm920t_write_phys_memory(struct target *target,
                uint32_t address, uint32_t size,
-               uint32_t count, uint8_t *buffer)
+               uint32_t count, const uint8_t *buffer)
 {
        struct arm920t_common *arm920t = target_to_arm920(target);
 
@@ -556,7 +610,7 @@ static int arm920t_write_phys_memory(struct target *target,
 
 /** Writes a buffer, in the specified word size, with current MMU settings. */
 int arm920t_write_memory(struct target *target, uint32_t address,
-               uint32_t size, uint32_t count, uint8_t *buffer)
+               uint32_t size, uint32_t count, const uint8_t *buffer)
 {
        int retval;
        const uint32_t cache_mask = ~0x1f; /* cache line size : 32 byte */
@@ -841,7 +895,6 @@ COMMAND_HANDLER(arm920t_handle_read_cache_command)
        uint32_t C15_C_D_Ind, C15_C_I_Ind;
        int i;
        FILE *output;
-       struct arm920t_cache_line d_cache[8][64], i_cache[8][64];
        int segment, index_t;
        struct reg *r;
 
@@ -950,8 +1003,6 @@ COMMAND_HANDLER(arm920t_handle_read_cache_command)
                                return retval;
                        }
 
-                       d_cache[segment][index_t].cam = regs[9];
-
                        /* mask LFSR[6] */
                        regs[9] &= 0xfffffffe;
                        fprintf(output, "\nsegment: %i, index: %i, CAM: 0x%8.8"
@@ -961,7 +1012,6 @@ COMMAND_HANDLER(arm920t_handle_read_cache_command)
 
                        for (i = 1; i < 9; i++)
                        {
-                                d_cache[segment][index_t].data[i] = regs[i];
                                 fprintf(output, "%i: 0x%8.8" PRIx32 "\n",
                                                i-1, regs[i]);
                        }
@@ -1058,8 +1108,6 @@ COMMAND_HANDLER(arm920t_handle_read_cache_command)
                                return retval;
                        }
 
-                       i_cache[segment][index_t].cam = regs[9];
-
                        /* mask LFSR[6] */
                        regs[9] &= 0xfffffffe;
                        fprintf(output, "\nsegment: %i, index: %i, "
@@ -1069,7 +1117,6 @@ COMMAND_HANDLER(arm920t_handle_read_cache_command)
 
                        for (i = 1; i < 9; i++)
                        {
-                                i_cache[segment][index_t].data[i] = regs[i];
                                 fprintf(output, "%i: 0x%8.8" PRIx32 "\n",
                                                i-1, regs[i]);
                        }
@@ -1103,7 +1150,10 @@ COMMAND_HANDLER(arm920t_handle_read_cache_command)
        fclose(output);
 
        if (!is_arm_mode(armv4_5->core_mode))
+       {
+               LOG_ERROR("not a valid arm core mode - communication failure?");
                return ERROR_FAIL;
+       }
 
        /* force writeback of the valid data */
        r = armv4_5->core_cache->reg_list;
@@ -1430,7 +1480,10 @@ COMMAND_HANDLER(arm920t_handle_read_mmu_command)
        fclose(output);
 
        if (!is_arm_mode(armv4_5->core_mode))
+       {
+               LOG_ERROR("not a valid arm core mode - communication failure?");
                return ERROR_FAIL;
+       }
 
        /* force writeback of the valid data */
        r = armv4_5->core_cache->reg_list;
Open On-Chip Debugger

Linking to existing account procedure

If you already have an account and want to add another login method you MUST first sign in with your existing account and then change URL to read https://review.openocd.org/login/?link to get to this page again but this time it'll work for linking. Thank you.

SSH host keys fingerprints

1024 SHA256:YKx8b7u5ZWdcbp7/4AeXNaqElP49m6QrwfXaqQGJAOk gerrit-code-review@openocd.zylin.com (DSA)
384 SHA256:jHIbSQa4REvwCFG4cq5LBlBLxmxSqelQPem/EXIrxjk gerrit-code-review@openocd.org (ECDSA)
521 SHA256:UAOPYkU9Fjtcao0Ul/Rrlnj/OsQvt+pgdYSZ4jOYdgs gerrit-code-review@openocd.org (ECDSA)
256 SHA256:A13M5QlnozFOvTllybRZH6vm7iSt0XLxbA48yfc2yfY gerrit-code-review@openocd.org (ECDSA)
256 SHA256:spYMBqEYoAOtK7yZBrcwE8ZpYt6b68Cfh9yEVetvbXg gerrit-code-review@openocd.org (ED25519)
+--[ED25519 256]--+
|=..              |
|+o..   .         |
|*.o   . .        |
|+B . . .         |
|Bo. = o S        |
|Oo.+ + =         |
|oB=.* = . o      |
| =+=.+   + E     |
|. .=o   . o      |
+----[SHA256]-----+
2048 SHA256:0Onrb7/PHjpo6iVZ7xQX2riKN83FJ3KGU0TvI0TaFG4 gerrit-code-review@openocd.zylin.com (RSA)