ARM11: recognize ARM11 MPCore

[openocd.git] / src / target / arm920t.c

diff --git a/src/target/arm920t.c b/src/target/arm920t.c
index 6a005d6d8ca76d5b7b497be13598f3c6ffec2f0d..c5b7c88dcdca3fea2dfe171b1bfc494c474280da 100644 (file)
--- a/src/target/arm920t.c
+++ b/src/target/arm920t.c
@@ -25,6 +25,7 @@
 #include <helper/time_support.h>
 #include "target_type.h"
 #include "register.h"
+#include "arm_opcodes.h"
 
 
 /*
@@ -448,14 +449,8 @@ int arm920t_arch_state(struct target *target)
 
        armv4_5 = &arm920t->arm7_9_common.armv4_5_common;
 
-       LOG_USER("target halted in %s state due to %s, current mode: %s\n"
-                       "cpsr: 0x%8.8" PRIx32 " pc: 0x%8.8" PRIx32 "\n"
-                       "MMU: %s, D-Cache: %s, I-Cache: %s",
-                        arm_state_strings[armv4_5->core_state],
-                        Jim_Nvp_value2name_simple(nvp_target_debug_reason, target->debug_reason)->name,
-                        arm_mode_name(armv4_5->core_mode),
-                        buf_get_u32(armv4_5->cpsr->value, 0, 32),
-                        buf_get_u32(armv4_5->core_cache->reg_list[15].value, 0, 32),
+       arm_arch_state(target);
+       LOG_USER("MMU: %s, D-Cache: %s, I-Cache: %s",
                         state[arm920t->armv4_5_mmu.mmu_enabled],
                         state[arm920t->armv4_5_mmu.armv4_5_cache.d_u_cache_enabled],
                         state[arm920t->armv4_5_mmu.armv4_5_cache.i_cache_enabled]);
@@ -1452,7 +1447,7 @@ struct target_type arm920t_target =
        .deassert_reset = arm7_9_deassert_reset,
        .soft_reset_halt = arm920t_soft_reset_halt,
 
-       .get_gdb_reg_list = armv4_5_get_gdb_reg_list,
+       .get_gdb_reg_list = arm_get_gdb_reg_list,
 
        .read_memory = arm920t_read_memory,
        .write_memory = arm920t_write_memory,