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- correct corrupt target configs
[openocd.git] / src / target / arm920t.c
diff --git a/src/target/arm920t.c b/src/target/arm920t.c
index 67ffb3877a6b3429875f1598408bfd2940dc6902..b22a8c2bad384d4e166ed4c9b28918bf534d99d7 100644 (file)
--- a/src/target/arm920t.c
+++ b/src/target/arm920t.c
@@ -233,6 +233,7 @@ int arm920t_write_cp15_physical(target_t *target, int reg_addr, u32 value)
 
 int arm920t_execute_cp15(target_t *target, u32 cp15_opcode, u32 arm_opcode)
 {
+       int retval;
        armv4_5_common_t *armv4_5 = target->arch_info;
        arm7_9_common_t *arm7_9 = armv4_5->arch_info;
        arm_jtag_t *jtag_info = &arm7_9->jtag_info;
@@ -292,12 +293,14 @@ int arm920t_execute_cp15(target_t *target, u32 cp15_opcode, u32 arm_opcode)
 
        arm9tdmi_clock_out(jtag_info, arm_opcode, 0, NULL, 0);
        arm9tdmi_clock_out(jtag_info, ARMV4_5_NOP, 0, NULL, 1);
-       arm7_9_execute_sys_speed(target);
+       retval = arm7_9_execute_sys_speed(target);
+       if (retval != ERROR_OK)
+               return retval;
        
-       if (jtag_execute_queue() != ERROR_OK)
+       if ((retval = jtag_execute_queue()) != ERROR_OK)
        {
                LOG_ERROR("failed executing JTAG queue, exiting");
-               exit(-1);
+               return retval;
        }
        
        return ERROR_OK;
@@ -625,13 +628,17 @@ int arm920t_write_memory(struct target_s *target, u32 address, u32 size, u32 cou
 
 int arm920t_soft_reset_halt(struct target_s *target)
 {
+       int retval = ERROR_OK;
        armv4_5_common_t *armv4_5 = target->arch_info;
        arm7_9_common_t *arm7_9 = armv4_5->arch_info;
        arm9tdmi_common_t *arm9tdmi = arm7_9->arch_info;
        arm920t_common_t *arm920t = arm9tdmi->arch_info;
        reg_t *dbg_stat = &arm7_9->eice_cache->reg_list[EICE_DBG_STAT];
        
-       target_halt(target);
+       if((retval = target_halt(target)) != ERROR_OK)
+       {
+               return retval;
+       }
        
        long long then=timeval_ms();
        int timeout;
@@ -640,7 +647,10 @@ int arm920t_soft_reset_halt(struct target_s *target)
                if (buf_get_u32(dbg_stat->value, EICE_DBG_STATUS_DBGACK, 1) == 0)
                {
                        embeddedice_read_reg(dbg_stat);
-                       jtag_execute_queue();
+                       if((retval = jtag_execute_queue()) != ERROR_OK)
+                       {
+                               return retval;
+                       }
                } else
                {
                        break;
@@ -680,7 +690,10 @@ int arm920t_soft_reset_halt(struct target_s *target)
        arm920t->armv4_5_mmu.armv4_5_cache.d_u_cache_enabled = 0;
        arm920t->armv4_5_mmu.armv4_5_cache.i_cache_enabled = 0;
 
-       target_call_event_callbacks(target, TARGET_EVENT_HALTED);
+       if((retval = target_call_event_callbacks(target, TARGET_EVENT_HALTED)) != ERROR_OK)
+       {
+               return retval;
+       }
        
        return ERROR_OK;
 }
@@ -770,11 +783,12 @@ int arm920t_register_commands(struct command_context_s *cmd_ctx)
        register_command(cmd_ctx, arm920t_cmd, "read_cache", arm920t_handle_read_cache_command, COMMAND_EXEC, "display I/D cache content");
        register_command(cmd_ctx, arm920t_cmd, "read_mmu", arm920t_handle_read_mmu_command, COMMAND_EXEC, "display I/D mmu content");
 
-       return ERROR_OK;
+       return retval;
 }
 
 int arm920t_handle_read_cache_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc)
 {
+       int retval = ERROR_OK;
        target_t *target = get_current_target(cmd_ctx);
        armv4_5_common_t *armv4_5;
        arm7_9_common_t *arm7_9;
@@ -816,7 +830,10 @@ int arm920t_handle_read_cache_command(struct command_context_s *cmd_ctx, char *c
        
        /* disable MMU and Caches */
        arm920t_read_cp15_physical(target, ARM920T_CP15_PHYS_ADDR(0, 0x1, 0), &cp15_ctrl);
-       jtag_execute_queue();
+       if((retval = jtag_execute_queue()) != ERROR_OK)
+       {
+               return retval;
+       }
        cp15_ctrl_saved = cp15_ctrl;
        cp15_ctrl &= ~(ARMV4_5_MMU_ENABLED | ARMV4_5_D_U_CACHE_ENABLED | ARMV4_5_I_CACHE_ENABLED);
        arm920t_write_cp15_physical(target, ARM920T_CP15_PHYS_ADDR(0, 0x1, 0), cp15_ctrl);
@@ -876,7 +893,10 @@ int arm920t_handle_read_cache_command(struct command_context_s *cmd_ctx, char *c
 
                        /* read D RAM and CAM content */
                        arm9tdmi_read_core_regs(target, 0x3fe, regs_p);
-                       jtag_execute_queue();
+                       if((retval = jtag_execute_queue()) != ERROR_OK)
+                       {
+                               return retval;
+                       }
 
                        d_cache[segment][index].cam = regs[9];
                        
@@ -959,7 +979,10 @@ int arm920t_handle_read_cache_command(struct command_context_s *cmd_ctx, char *c
 
                        /* read I RAM and CAM content */
                        arm9tdmi_read_core_regs(target, 0x3fe, regs_p);
-                       jtag_execute_queue();
+                       if((retval = jtag_execute_queue()) != ERROR_OK)
+                       {
+                               return retval;
+                       }
 
                        i_cache[segment][index].cam = regs[9];
                        
@@ -1019,6 +1042,7 @@ int arm920t_handle_read_cache_command(struct command_context_s *cmd_ctx, char *c
 
 int arm920t_handle_read_mmu_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc)
 {
+       int retval = ERROR_OK;
        target_t *target = get_current_target(cmd_ctx);
        armv4_5_common_t *armv4_5;
        arm7_9_common_t *arm7_9;
@@ -1060,14 +1084,20 @@ int arm920t_handle_read_mmu_command(struct command_context_s *cmd_ctx, char *cmd
        
        /* disable MMU and Caches */
        arm920t_read_cp15_physical(target, ARM920T_CP15_PHYS_ADDR(0, 0x1, 0), &cp15_ctrl);
-       jtag_execute_queue();
+       if((retval = jtag_execute_queue()) != ERROR_OK)
+       {
+               return retval;
+       }
        cp15_ctrl_saved = cp15_ctrl;
        cp15_ctrl &= ~(ARMV4_5_MMU_ENABLED | ARMV4_5_D_U_CACHE_ENABLED | ARMV4_5_I_CACHE_ENABLED);
        arm920t_write_cp15_physical(target, ARM920T_CP15_PHYS_ADDR(0, 0x1, 0), cp15_ctrl);
 
        /* read CP15 test state register */ 
        arm920t_read_cp15_physical(target, ARM920T_CP15_PHYS_ADDR(0, 0xf, 0), &cp15c15);
-       jtag_execute_queue();
+       if((retval = jtag_execute_queue()) != ERROR_OK)
+       {
+               return retval;
+       }
 
        /* prepare reading D TLB content 
         * */
@@ -1085,7 +1115,10 @@ int arm920t_handle_read_mmu_command(struct command_context_s *cmd_ctx, char *cmd
        
        /* read D TLB lockdown stored to r1 */
        arm9tdmi_read_core_regs(target, 0x2, regs_p);
-       jtag_execute_queue();
+       if((retval = jtag_execute_queue()) != ERROR_OK)
+       {
+               return retval;
+       }
        Dlockdown = regs[1];
        
        for (victim = 0; victim < 64; victim += 8)
@@ -1111,7 +1144,10 @@ int arm920t_handle_read_mmu_command(struct command_context_s *cmd_ctx, char *cmd
                
                /* read D TLB CAM content stored to r2-r9 */
                arm9tdmi_read_core_regs(target, 0x3fc, regs_p);
-               jtag_execute_queue();
+               if((retval = jtag_execute_queue()) != ERROR_OK)
+               {
+                       return retval;
+               }
                
                for (i = 0; i < 8; i++)
                        d_tlb[victim + i].cam = regs[i + 2]; 
@@ -1143,7 +1179,10 @@ int arm920t_handle_read_mmu_command(struct command_context_s *cmd_ctx, char *cmd
                
                /* read D TLB RAM content stored to r2 and r3 */
                arm9tdmi_read_core_regs(target, 0xc, regs_p);
-               jtag_execute_queue();
+               if((retval = jtag_execute_queue()) != ERROR_OK)
+               {
+                       return retval;
+               }
 
                d_tlb[victim].ram1 = regs[2]; 
                d_tlb[victim].ram2 = regs[3]; 
@@ -1172,7 +1211,10 @@ int arm920t_handle_read_mmu_command(struct command_context_s *cmd_ctx, char *cmd
        
        /* read I TLB lockdown stored to r1 */
        arm9tdmi_read_core_regs(target, 0x2, regs_p);
-       jtag_execute_queue();
+       if((retval = jtag_execute_queue()) != ERROR_OK)
+       {
+               return retval;
+       }
        Ilockdown = regs[1];
        
        for (victim = 0; victim < 64; victim += 8)
@@ -1198,7 +1240,10 @@ int arm920t_handle_read_mmu_command(struct command_context_s *cmd_ctx, char *cmd
                
                /* read I TLB CAM content stored to r2-r9 */
                arm9tdmi_read_core_regs(target, 0x3fc, regs_p);
-               jtag_execute_queue();
+               if((retval = jtag_execute_queue()) != ERROR_OK)
+               {
+                       return retval;
+               }
                
                for (i = 0; i < 8; i++)
                        i_tlb[i + victim].cam = regs[i + 2]; 
@@ -1230,7 +1275,10 @@ int arm920t_handle_read_mmu_command(struct command_context_s *cmd_ctx, char *cmd
                
                /* read I TLB RAM content stored to r2 and r3 */
                arm9tdmi_read_core_regs(target, 0xc, regs_p);
-               jtag_execute_queue();
+               if((retval = jtag_execute_queue()) != ERROR_OK)
+               {
+                       return retval;
+               }
 
                i_tlb[victim].ram1 = regs[2]; 
                i_tlb[victim].ram2 = regs[3]; 
@@ -1317,7 +1365,10 @@ int arm920t_handle_cp15_command(struct command_context_s *cmd_ctx, char *cmd, ch
                                command_print(cmd_ctx, "couldn't access reg %i", address);
                                return ERROR_OK;
                        }
-                       jtag_execute_queue();
+                       if((retval = jtag_execute_queue()) != ERROR_OK)
+                       {
+                               return retval;
+                       }
                        
                        command_print(cmd_ctx, "%i: %8.8x", address, value);
                }
@@ -1500,12 +1551,3 @@ int arm920t_handle_mw_phys_command(command_context_t *cmd_ctx, char *cmd, char *
        
        return armv4_5_mmu_handle_mw_phys_command(cmd_ctx, cmd, args, argc, target, &arm920t->armv4_5_mmu);
 }
-
-
-
-/*
- * Local Variables: ***
- * c-basic-offset: 4 ***
- * tab-width: 4 ***
- * End: ***
- */
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