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- Fixes '[<>]' whitespace
[openocd.git] / src / target / arm920t.c
diff --git a/src/target/arm920t.c b/src/target/arm920t.c
index 8fe2cc4076c5b15bef6ab8a5cedb62dd7b55cfb3..92cee83c5687172bd128e97e0e6ce0d7d452a640 100644 (file)
--- a/src/target/arm920t.c
+++ b/src/target/arm920t.c
@@ -31,8 +31,6 @@
 #endif
 
 /* cli handling */
-int arm920t_register_commands(struct command_context_s *cmd_ctx);
-
 int arm920t_handle_cp15_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc);
 int arm920t_handle_cp15i_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc);
 int arm920t_handle_virt2phys_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc);
@@ -47,10 +45,6 @@ int arm920t_handle_read_mmu_command(struct command_context_s *cmd_ctx, char *cmd
 int arm920t_target_create(struct target_s *target, Jim_Interp *interp);
 int arm920t_init_target(struct command_context_s *cmd_ctx, struct target_s *target);
 int arm920t_quit(void);
-int arm920t_arch_state(struct target_s *target);
-int arm920t_read_memory(struct target_s *target, u32 address, u32 size, u32 count, uint8_t *buffer);
-int arm920t_write_memory(struct target_s *target, u32 address, u32 size, u32 count, uint8_t *buffer);
-int arm920t_soft_reset_halt(struct target_s *target);
 
 #define ARM920T_CP15_PHYS_ADDR(x, y, z) ((x << 5) | (y << 1) << (z))
 
@@ -93,7 +87,7 @@ target_type_t arm920t_target =
        .quit = arm920t_quit
 };
 
-int arm920t_read_cp15_physical(target_t *target, int reg_addr, u32 *value)
+int arm920t_read_cp15_physical(target_t *target, int reg_addr, uint32_t *value)
 {
        armv4_5_common_t *armv4_5 = target->arch_info;
        arm7_9_common_t *arm7_9 = armv4_5->arch_info;
@@ -133,7 +127,7 @@ int arm920t_read_cp15_physical(target_t *target, int reg_addr, u32 *value)
 
        jtag_add_dr_scan(4, fields, jtag_get_end_state());
 
-       jtag_add_callback(arm_le_to_h_u32, (uint8_t *)value);
+       jtag_add_callback(arm_le_to_h_u32, (jtag_callback_data_t)value);
 
        #ifdef _DEBUG_INSTRUCTION_EXECUTION_
        jtag_execute_queue();
@@ -143,7 +137,7 @@ int arm920t_read_cp15_physical(target_t *target, int reg_addr, u32 *value)
        return ERROR_OK;
 }
 
-int arm920t_write_cp15_physical(target_t *target, int reg_addr, u32 value)
+int arm920t_write_cp15_physical(target_t *target, int reg_addr, uint32_t value)
 {
        armv4_5_common_t *armv4_5 = target->arch_info;
        arm7_9_common_t *arm7_9 = armv4_5->arch_info;
@@ -189,7 +183,7 @@ int arm920t_write_cp15_physical(target_t *target, int reg_addr, u32 value)
        return ERROR_OK;
 }
 
-int arm920t_execute_cp15(target_t *target, u32 cp15_opcode, u32 arm_opcode)
+int arm920t_execute_cp15(target_t *target, uint32_t cp15_opcode, uint32_t arm_opcode)
 {
        int retval;
        armv4_5_common_t *armv4_5 = target->arch_info;
@@ -244,12 +238,12 @@ int arm920t_execute_cp15(target_t *target, u32 cp15_opcode, u32 arm_opcode)
        return ERROR_OK;
 }
 
-int arm920t_read_cp15_interpreted(target_t *target, u32 cp15_opcode, u32 address, u32 *value)
+int arm920t_read_cp15_interpreted(target_t *target, uint32_t cp15_opcode, uint32_t address, uint32_t *value)
 {
        armv4_5_common_t *armv4_5 = target->arch_info;
-       u32* regs_p[1];
-       u32 regs[2];
-       u32 cp15c15 = 0x0;
+       uint32_t* regs_p[1];
+       uint32_t regs[2];
+       uint32_t cp15c15 = 0x0;
 
        /* load address into R1 */
        regs[1] = address;
@@ -287,11 +281,11 @@ int arm920t_read_cp15_interpreted(target_t *target, u32 cp15_opcode, u32 address
        return ERROR_OK;
 }
 
-int arm920t_write_cp15_interpreted(target_t *target, u32 cp15_opcode, u32 value, u32 address)
+int arm920t_write_cp15_interpreted(target_t *target, uint32_t cp15_opcode, uint32_t value, uint32_t address)
 {
-       u32 cp15c15 = 0x0;
+       uint32_t cp15c15 = 0x0;
        armv4_5_common_t *armv4_5 = target->arch_info;
-       u32 regs[2];
+       uint32_t regs[2];
 
        /* load value, address into R0, R1 */
        regs[0] = value;
@@ -325,10 +319,10 @@ int arm920t_write_cp15_interpreted(target_t *target, u32 cp15_opcode, u32 value,
        return ERROR_OK;
 }
 
-u32 arm920t_get_ttb(target_t *target)
+uint32_t arm920t_get_ttb(target_t *target)
 {
        int retval;
-       u32 ttb = 0x0;
+       uint32_t ttb = 0x0;
 
        if ((retval = arm920t_read_cp15_interpreted(target, 0xeebf0f51, 0x0, &ttb)) != ERROR_OK)
                return retval;
@@ -338,7 +332,7 @@ u32 arm920t_get_ttb(target_t *target)
 
 void arm920t_disable_mmu_caches(target_t *target, int mmu, int d_u_cache, int i_cache)
 {
-       u32 cp15_control;
+       uint32_t cp15_control;
 
        /* read cp15 control register */
        arm920t_read_cp15_physical(target, 0x2, &cp15_control);
@@ -358,7 +352,7 @@ void arm920t_disable_mmu_caches(target_t *target, int mmu, int d_u_cache, int i_
 
 void arm920t_enable_mmu_caches(target_t *target, int mmu, int d_u_cache, int i_cache)
 {
-       u32 cp15_control;
+       uint32_t cp15_control;
 
        /* read cp15 control register */
        arm920t_read_cp15_physical(target, 0x2, &cp15_control);
@@ -378,7 +372,7 @@ void arm920t_enable_mmu_caches(target_t *target, int mmu, int d_u_cache, int i_c
 
 void arm920t_post_debug_entry(target_t *target)
 {
-       u32 cp15c15;
+       uint32_t cp15c15;
        armv4_5_common_t *armv4_5 = target->arch_info;
        arm7_9_common_t *arm7_9 = armv4_5->arch_info;
        arm9tdmi_common_t *arm9tdmi = arm7_9->arch_info;
@@ -387,11 +381,11 @@ void arm920t_post_debug_entry(target_t *target)
        /* examine cp15 control reg */
        arm920t_read_cp15_physical(target, 0x2, &arm920t->cp15_control_reg);
        jtag_execute_queue();
-       LOG_DEBUG("cp15_control_reg: %8.8x", arm920t->cp15_control_reg);
+       LOG_DEBUG("cp15_control_reg: %8.8" PRIx32 "", arm920t->cp15_control_reg);
 
        if (arm920t->armv4_5_mmu.armv4_5_cache.ctype == -1)
        {
-               u32 cache_type_reg;
+               uint32_t cache_type_reg;
                /* identify caches */
                arm920t_read_cp15_physical(target, 0x1, &cache_type_reg);
                jtag_execute_queue();
@@ -408,7 +402,7 @@ void arm920t_post_debug_entry(target_t *target)
        arm920t_read_cp15_interpreted(target, 0xee160f10, 0x0, &arm920t->d_far);
        arm920t_read_cp15_interpreted(target, 0xee160f30, 0x0, &arm920t->i_far);
 
-       LOG_DEBUG("D FSR: 0x%8.8x, D FAR: 0x%8.8x, I FSR: 0x%8.8x, I FAR: 0x%8.8x",
+       LOG_DEBUG("D FSR: 0x%8.8" PRIx32 ", D FAR: 0x%8.8" PRIx32 ", I FSR: 0x%8.8" PRIx32 ", I FAR: 0x%8.8" PRIx32 "",
                arm920t->d_fsr, arm920t->d_far, arm920t->i_fsr, arm920t->i_far);
 
        if (arm920t->preserve_cache)
@@ -424,7 +418,7 @@ void arm920t_post_debug_entry(target_t *target)
 
 void arm920t_pre_restore_context(target_t *target)
 {
-       u32 cp15c15;
+       uint32_t cp15c15;
        armv4_5_common_t *armv4_5 = target->arch_info;
        arm7_9_common_t *arm7_9 = armv4_5->arch_info;
        arm9tdmi_common_t *arm9tdmi = arm7_9->arch_info;
@@ -504,7 +498,7 @@ int arm920t_arch_state(struct target_s *target)
        }
 
        LOG_USER(       "target halted in %s state due to %s, current mode: %s\n"
-                       "cpsr: 0x%8.8x pc: 0x%8.8x\n"
+                       "cpsr: 0x%8.8" PRIx32 " pc: 0x%8.8" PRIx32 "\n"
                        "MMU: %s, D-Cache: %s, I-Cache: %s",
                         armv4_5_state_strings[armv4_5->core_state],
                         Jim_Nvp_value2name_simple(nvp_target_debug_reason, target->debug_reason)->name,
@@ -518,7 +512,7 @@ int arm920t_arch_state(struct target_s *target)
        return ERROR_OK;
 }
 
-int arm920t_read_memory(struct target_s *target, u32 address, u32 size, u32 count, uint8_t *buffer)
+int arm920t_read_memory(struct target_s *target, uint32_t address, uint32_t size, uint32_t count, uint8_t *buffer)
 {
        int retval;
 
@@ -527,7 +521,7 @@ int arm920t_read_memory(struct target_s *target, u32 address, u32 size, u32 coun
        return retval;
 }
 
-int arm920t_write_memory(struct target_s *target, u32 address, u32 size, u32 count, uint8_t *buffer)
+int arm920t_write_memory(struct target_s *target, uint32_t address, uint32_t size, uint32_t count, uint8_t *buffer)
 {
        int retval;
        armv4_5_common_t *armv4_5 = target->arch_info;
@@ -543,7 +537,7 @@ int arm920t_write_memory(struct target_s *target, u32 address, u32 size, u32 cou
                if (arm920t->armv4_5_mmu.armv4_5_cache.d_u_cache_enabled)
                {
                        LOG_DEBUG("D-Cache enabled, writing through to main memory");
-                       u32 pa, cb, ap;
+                       uint32_t pa, cb, ap;
                        int type, domain;
 
                        pa = armv4_5_mmu_translate_va(target, &arm920t->armv4_5_mmu, address, &type, &cb, &domain, &ap);
@@ -578,9 +572,9 @@ int arm920t_soft_reset_halt(struct target_s *target)
                return retval;
        }
 
-       long long then=timeval_ms();
+       long long then = timeval_ms();
        int timeout;
-       while (!(timeout=((timeval_ms()-then)>1000)))
+       while (!(timeout = ((timeval_ms()-then) > 1000)))
        {
                if (buf_get_u32(dbg_stat->value, EICE_DBG_STATUS_DBGACK, 1) == 0)
                {
@@ -593,7 +587,7 @@ int arm920t_soft_reset_halt(struct target_s *target)
                {
                        break;
                }
-               if (debug_level>=3)
+               if (debug_level >= 3)
                {
                        /* do not eat all CPU, time out after 1 se*/
                        alive_sleep(100);
@@ -731,11 +725,11 @@ int arm920t_handle_read_cache_command(struct command_context_s *cmd_ctx, char *c
        arm9tdmi_common_t *arm9tdmi;
        arm920t_common_t *arm920t;
        arm_jtag_t *jtag_info;
-       u32 cp15c15;
-       u32 cp15_ctrl, cp15_ctrl_saved;
-       u32 regs[16];
-       u32 *regs_p[16];
-       u32 C15_C_D_Ind, C15_C_I_Ind;
+       uint32_t cp15c15;
+       uint32_t cp15_ctrl, cp15_ctrl_saved;
+       uint32_t regs[16];
+       uint32_t *regs_p[16];
+       uint32_t C15_C_D_Ind, C15_C_I_Ind;
        int i;
        FILE *output;
        arm920t_cache_line_t d_cache[8][64], i_cache[8][64];
@@ -838,12 +832,12 @@ int arm920t_handle_read_cache_command(struct command_context_s *cmd_ctx, char *c
 
                        /* mask LFSR[6] */
                        regs[9] &= 0xfffffffe;
-                       fprintf(output, "\nsegment: %i, index: %i, CAM: 0x%8.8x, content (%s):\n", segment, index, regs[9], (regs[9] & 0x10) ? "valid" : "invalid");
+                       fprintf(output, "\nsegment: %i, index: %i, CAM: 0x%8.8" PRIx32 ", content (%s):\n", segment, index, regs[9], (regs[9] & 0x10) ? "valid" : "invalid");
 
                        for (i = 1; i < 9; i++)
                        {
                                 d_cache[segment][index].data[i] = regs[i];
-                                fprintf(output, "%i: 0x%8.8x\n", i-1, regs[i]);
+                                fprintf(output, "%i: 0x%8.8" PRIx32 "\n", i-1, regs[i]);
                        }
 
                }
@@ -924,12 +918,12 @@ int arm920t_handle_read_cache_command(struct command_context_s *cmd_ctx, char *c
 
                        /* mask LFSR[6] */
                        regs[9] &= 0xfffffffe;
-                       fprintf(output, "\nsegment: %i, index: %i, CAM: 0x%8.8x, content (%s):\n", segment, index, regs[9], (regs[9] & 0x10) ? "valid" : "invalid");
+                       fprintf(output, "\nsegment: %i, index: %i, CAM: 0x%8.8" PRIx32 ", content (%s):\n", segment, index, regs[9], (regs[9] & 0x10) ? "valid" : "invalid");
 
                        for (i = 1; i < 9; i++)
                        {
                                 i_cache[segment][index].data[i] = regs[i];
-                                fprintf(output, "%i: 0x%8.8x\n", i-1, regs[i]);
+                                fprintf(output, "%i: 0x%8.8" PRIx32 "\n", i-1, regs[i]);
                        }
                }
 
@@ -983,13 +977,13 @@ int arm920t_handle_read_mmu_command(struct command_context_s *cmd_ctx, char *cmd
        arm9tdmi_common_t *arm9tdmi;
        arm920t_common_t *arm920t;
        arm_jtag_t *jtag_info;
-       u32 cp15c15;
-       u32 cp15_ctrl, cp15_ctrl_saved;
-       u32 regs[16];
-       u32 *regs_p[16];
+       uint32_t cp15c15;
+       uint32_t cp15_ctrl, cp15_ctrl_saved;
+       uint32_t regs[16];
+       uint32_t *regs_p[16];
        int i;
        FILE *output;
-       u32 Dlockdown, Ilockdown;
+       uint32_t Dlockdown, Ilockdown;
        arm920t_tlb_entry_t d_tlb[64], i_tlb[64];
        int victim;
 
@@ -1232,13 +1226,13 @@ int arm920t_handle_read_mmu_command(struct command_context_s *cmd_ctx, char *cmd
        fprintf(output, "D TLB content:\n");
        for (i = 0; i < 64; i++)
        {
-               fprintf(output, "%i: 0x%8.8x 0x%8.8x 0x%8.8x %s\n", i, d_tlb[i].cam, d_tlb[i].ram1, d_tlb[i].ram2, (d_tlb[i].cam & 0x20) ? "(valid)" : "(invalid)");
+               fprintf(output, "%i: 0x%8.8" PRIx32 " 0x%8.8" PRIx32 " 0x%8.8" PRIx32 " %s\n", i, d_tlb[i].cam, d_tlb[i].ram1, d_tlb[i].ram2, (d_tlb[i].cam & 0x20) ? "(valid)" : "(invalid)");
        }
 
        fprintf(output, "\n\nI TLB content:\n");
        for (i = 0; i < 64; i++)
        {
-               fprintf(output, "%i: 0x%8.8x 0x%8.8x 0x%8.8x %s\n", i, i_tlb[i].cam, i_tlb[i].ram1, i_tlb[i].ram2, (i_tlb[i].cam & 0x20) ? "(valid)" : "(invalid)");
+               fprintf(output, "%i: 0x%8.8" PRIx32 " 0x%8.8" PRIx32 " 0x%8.8" PRIx32 " %s\n", i, i_tlb[i].cam, i_tlb[i].ram1, i_tlb[i].ram2, (i_tlb[i].cam & 0x20) ? "(valid)" : "(invalid)");
        }
 
        command_print(cmd_ctx, "mmu content successfully output to %s", args[0]);
@@ -1293,7 +1287,7 @@ int arm920t_handle_cp15_command(struct command_context_s *cmd_ctx, char *cmd, ch
 
                if (argc == 1)
                {
-                       u32 value;
+                       uint32_t value;
                        if ((retval = arm920t_read_cp15_physical(target, address, &value)) != ERROR_OK)
                        {
                                command_print(cmd_ctx, "couldn't access reg %i", address);
@@ -1304,17 +1298,17 @@ int arm920t_handle_cp15_command(struct command_context_s *cmd_ctx, char *cmd, ch
                                return retval;
                        }
 
-                       command_print(cmd_ctx, "%i: %8.8x", address, value);
+                       command_print(cmd_ctx, "%i: %8.8" PRIx32 "", address, value);
                }
                else if (argc == 2)
                {
-                       u32 value = strtoul(args[1], NULL, 0);
+                       uint32_t value = strtoul(args[1], NULL, 0);
                        if ((retval = arm920t_write_cp15_physical(target, address, value)) != ERROR_OK)
                        {
                                command_print(cmd_ctx, "couldn't access reg %i", address);
                                return ERROR_OK;
                        }
-                       command_print(cmd_ctx, "%i: %8.8x", address, value);
+                       command_print(cmd_ctx, "%i: %8.8" PRIx32 "", address, value);
                }
        }
 
@@ -1348,39 +1342,39 @@ int arm920t_handle_cp15i_command(struct command_context_s *cmd_ctx, char *cmd, c
        /* one or more argument, access a single register (write if second argument is given */
        if (argc >= 1)
        {
-               u32 opcode = strtoul(args[0], NULL, 0);
+               uint32_t opcode = strtoul(args[0], NULL, 0);
 
                if (argc == 1)
                {
-                       u32 value;
+                       uint32_t value;
                        if ((retval = arm920t_read_cp15_interpreted(target, opcode, 0x0, &value)) != ERROR_OK)
                        {
-                               command_print(cmd_ctx, "couldn't execute %8.8x", opcode);
+                               command_print(cmd_ctx, "couldn't execute %8.8" PRIx32 "", opcode);
                                return ERROR_OK;
                        }
 
-                       command_print(cmd_ctx, "%8.8x: %8.8x", opcode, value);
+                       command_print(cmd_ctx, "%8.8" PRIx32 ": %8.8" PRIx32 "", opcode, value);
                }
                else if (argc == 2)
                {
-                       u32 value = strtoul(args[1], NULL, 0);
+                       uint32_t value = strtoul(args[1], NULL, 0);
                        if ((retval = arm920t_write_cp15_interpreted(target, opcode, value, 0)) != ERROR_OK)
                        {
-                               command_print(cmd_ctx, "couldn't execute %8.8x", opcode);
+                               command_print(cmd_ctx, "couldn't execute %8.8" PRIx32 "", opcode);
                                return ERROR_OK;
                        }
-                       command_print(cmd_ctx, "%8.8x: %8.8x", opcode, value);
+                       command_print(cmd_ctx, "%8.8" PRIx32 ": %8.8" PRIx32 "", opcode, value);
                }
                else if (argc == 3)
                {
-                       u32 value = strtoul(args[1], NULL, 0);
-                       u32 address = strtoul(args[2], NULL, 0);
+                       uint32_t value = strtoul(args[1], NULL, 0);
+                       uint32_t address = strtoul(args[2], NULL, 0);
                        if ((retval = arm920t_write_cp15_interpreted(target, opcode, value, address)) != ERROR_OK)
                        {
-                               command_print(cmd_ctx, "couldn't execute %8.8x", opcode);
+                               command_print(cmd_ctx, "couldn't execute %8.8" PRIx32 "", opcode);
                                return ERROR_OK;
                        }
-                       command_print(cmd_ctx, "%8.8x: %8.8x %8.8x", opcode, value, address);
+                       command_print(cmd_ctx, "%8.8" PRIx32 ": %8.8" PRIx32 " %8.8" PRIx32 "", opcode, value, address);
                }
        }
        else
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